Skip to main content
SpringerLink
Log in

Buffer memory optimization in DSP applications: An evolutionary approach

  • Conference paper
  • First Online:
Parallel Problem Solving from Nature — PPSN V (PPSN 1998)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1498))

Included in the following conference series:

Abstract

In the context of digital signal processing, synchronous data flow (SDF) graphs [12] are widely used for specification. For these, so called single appearance schedules provide program memory-optimal uniprocessor implementations. Here, buffer memory minimized schedules are explored among these using an Evolutionary Algorithm (EA). Whereas for a restricted class of graphs, there exist optimal polynomial algorithms, these are not exact and may provide poor results when applied to arbitrary, i.e., randomly generated graphs. We show that a careful EA implementation may outperform these algorithms by sometimes orders of magnitude.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. S. Bhattacharyya. Compiling data flow programs for digital signal processing. Technical Report UCB/ERL M94/52, Electronics Research Laboratory, UC Berkeley, July 1994.

    Google Scholar 

  2. S. S. Bhattacharyya, P. K. Murthy, and E. A. Lee. Software Synthesis from Dataflow Graphs. Kluwer Academic Publishers, Norwell, MA, 1996.

    MATH  Google Scholar 

  3. J. Buck, S. Ha, E.A. Lee, and D.G. Messerschmitt. Ptolemy: A framework for simulating and prototyping heterogeneous systems. International Journal on Computer Simulation, 4:155–182, 1991.

    Google Scholar 

  4. Lawrence Davis. Handbook of Genetic Algorithms, chapter 6, pages 72–90. Van Nostrand Reinhold, New York, 1991.

    Google Scholar 

  5. T. C. Denk and K. K. Parhi. Lower bounds on memory requirements for statically scheduled dsp programs. J. of VLSI Signal Processing, pages 247–264, 1996.

    Google Scholar 

  6. J. Fabri. Automatic Storage Optimization. UMI Research Press, 1982.

    Google Scholar 

  7. B. R. Fox and M. B. McMahon. Genetic operators for sequencing problems. In Gregory J. E. Rawlins, editor, Foundations of Genetic Algorithms, pages 284–300, Morgan Kaufmann, San Mateo, California, 1991.

    Google Scholar 

  8. M.R. Garey and D.S. Johnson. Computers and Intractability: A Guide to the Theory of NP-Completeness. Freeman, New York, 1979.

    MATH  Google Scholar 

  9. W.-C. Hsu. Register allocation and code scheduling for load/store architectures. Technical report, Department of Computer Science, University of Wisconsin at Madison, 1987.

    Google Scholar 

  10. D. J. Kolson, A. N. Nicolau, N. Dutt, and K. Kennedy. Optimal register assignment to loops for embedded code generation. ACM Trans. on Design Automation of Electronic Systems, 1(2):251–279, 1996.

    Article  Google Scholar 

  11. R. Lauwereins, M. Engels, J. A. Peperstraete, E. Steegmans, and J. Van Ginderdeuren. Grape: A CASE tool for digital signal parallel processing. IEEE ASSP Magazine, 7(2):32–43, April 1990.

    Article  Google Scholar 

  12. E.A. Lee and D.G. Messerschmitt. Synchronous dataflow. Proceedings of the IEEE, 75(9):1235–1245, 1987.

    Article  Google Scholar 

  13. P. Marwedel and G. Goossens (eds.). Code generation for embedded processors. Kluwer Academic Publishers, Norwell, MA, 1995.

    Google Scholar 

  14. S. Ritz, M. Pankert, and H. Meyr. High level software synthesis for signal processing systems. In Proc. Int. Conf. on Application-Specific Array Processors, pages 679–693, Berkeley, CA, 1992.

    Google Scholar 

  15. S. Ritz, M. Willems, and H. Meyr. Scheduling for optimum data memory compaction in block diagram oriented software synthesis. In Proceedings of the International Conference on Acoustics, Speech and Signal Processing, volume 4, pages 2651–2654, May 1995.

    Google Scholar 

  16. J. Teich, E. Zitzler, and S. S. Bhattacharyya. Optimized software synthesis for digital signal processing algorithms — an evolutionary approach. Technical Report 32, TIK, ETH Zurich Gloriastr. 35, CH-8092 Zurich, January 1998.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Institute TIK, Swiss Federal Institute of Technology, CH-8092, Zurich, Switzerland

    Jürgen Teich & Eckart Zitzler

  2. EE Dept. and UMIACS, University of Maryland, 20742, College Park, MD, USA

    Shuvra Bhattacharyya

Authors
  1. Jürgen Teich
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Eckart Zitzler
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Shuvra Bhattacharyya
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Agoston E. Eiben Thomas Bäck Marc Schoenauer Hans-Paul Schwefel

Rights and permissions

Reprints and permissions

Copyright information

© 1998 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Teich, J., Zitzler, E., Bhattacharyya, S. (1998). Buffer memory optimization in DSP applications: An evolutionary approach. In: Eiben, A.E., Bäck, T., Schoenauer, M., Schwefel, HP. (eds) Parallel Problem Solving from Nature — PPSN V. PPSN 1998. Lecture Notes in Computer Science, vol 1498. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0056930

Download citation

  • DOI: https://doi.org/10.1007/BFb0056930

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-65078-2

  • Online ISBN: 978-3-540-49672-4

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation