Abstract
This paper presents the results obtained by a new parallel procedure that generates the patterns for testing digital circuits when it is implemented in a shared-memory multiprocessor. The procedure is based on a new sequential algorithm which mixes both the Boolean difference and digital spectral techniques, thus being different from other parallel methods proposed up to now. First, it uses a static circuit partitioning procedure and later a dynamic load balancing scheme to distribute the load among the processors.
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References
Klenke, R.H., Williams, R.D., Aylor, J.H.: Parallel-Processing Techniques for Automatic Test Pattern Generation. IEEE Computer (January 1992) 71–84
Goel, P.: An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits. IEEE Transactions on Computers 30 (3) (1981) 215–222
Stanion, R.T., Bhattacharya, D., Sechen, C.: An Efficient Method for Generating Exhaustive Test Sets. IEEE Transactions on CAD 14 (12) (1995) 1516–1525
Fujiwara, H., Inoue, T.: Optimal Granularity of Test Generation in a Distributed System. IEEE Transactions on Computers-Aided Design 9 (8) (1990) 885–892
Patil, S., Banerjee, P.: Fault Partitioning Issues in an Integrated Parallel Test Generation/Fault Simulation Environment. International Test Conference (1989) 718–726
Gil, C., Ortega, J.: A Parallel Test Pattern Generator based on Spectral Techniques. 5th Euromicro on PDP, IEEE (1997) 199–204
Patil, S., Banerjee, P.: A Parallel Branch and Bound Algorithm for Test Generation. IEEE Trans. on CAD 9 (3) (1990) 313–322
Smith, S., Underwood, B., Mercer, M.R.: An Analysis of several approaches to Circuit Partitioning for Parallel Logic Simulation. Proceedings IEEE Int’l Conf. Computer-Design. CS Press, Los Alamitos, Calif. (1987) 664–667
Gil, C., J. Ortega: Algebraic Test-Pattern generation based on the Reed-Muller Spectrum. To appear in: IEE Proc. Computer and Digital Techniques 145 (4) (July 1998)
Gil, C., Ortega, J., Diaz, A.F., Montoya, M.G.: Meta-heuristics for Circuit Partitioning in Parallel Test Generation. First Workshop on Biologically Inspired Solutions to Parallel Processing Problems. Springer-Verlag, (1998)
Gil, C., Ortega, J.: Parallel Test Pattern Generation Using Circuit Partitioning and Spectral Techniques, 6th Euromicro on PDP, IEEE (1998) 264–270
Klenke, R. H., Williams, R. D., Aylor, J. H.: Parallelization Methods for Circuit Partitioning Based Parallel Automatic Test Pattern Generation. IEEE VLSI Test Symposium, (1993) 71–78.
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© 1998 Springer-Verlag Berlin Heidelberg
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Gil, C., Ortega, J., Luis Bernier, J., Dolores Gil, M. (1998). Parallel test pattern generation using circuit partitioning in a shared-memory multiprocessor. In: Kågström, B., Dongarra, J., Elmroth, E., Waśniewski, J. (eds) Applied Parallel Computing Large Scale Scientific and Industrial Problems. PARA 1998. Lecture Notes in Computer Science, vol 1541. Springer, Berlin, Heidelberg . https://doi.org/10.1007/BFb0095334
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DOI: https://doi.org/10.1007/BFb0095334
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