Interconnect synthesis for reconfigurable multi-FPGA architectures

Abstract

Most reconfigurable multi-FPGA architectures have a programmable interconnection network that can be reconfigured to implement different interconnection patterns between the FPGAs and memory devices on the board. Partitioning tools for such architectures must produce the necessary pin-assignments and interconnect configuration stream that correctly implement the partitioned design. We call this process Interconnect Synthesis for reconfigurable architectures.

The primary contribution of this paper is a interconnection synthesis technique that is independent of the reconfigurable interconnection architecture. We have developed an automatic interconnect synthesis tool that is based on Boolean satisfiability. The target interconnection architecture is modeled in an architecture specification language. The desired interconnections among the FPGAs are specified as in the form of a netlist. The tool automatically generates the pin-assignments and the required values for the configuration-inputs in the architecture specification. We modeled several reconfigurable architectures and performed interconnect synthesis for varying number of desired nets. We provide experimental results that demonstrate the effectiveness of the interconnection synthesis technique.

This work is supported in part by the US Air Force, Research Laboratory, WPAFB, contract #F33615-97-C-1043.