Scalable hardware-algorithms for binary prefix sums

Abstract

The main contribution of this work is to propose a number of broadcast-efficient VLSI architectures for computing the sum and the prefix sums of a w ^k-bit, k≥2, binary sequence using, as basic building blocks, linear arrays of at most w ² shift switches. An immediate consequence of this feature is that in our designs broadcasts are limited to buses of length at most w ² making them eminently practical. Using our design, the sum of a w ^k-bit binary sequence can be obtained in the time of 2k−2 broadcasts, using 2w ^k−2+O(w ^k−3) blocks, while the corresponding prefix sums can be computed in 3k−4 broadcasts using (k+2)w ^k−2+O(kw ^k−3) blocks.

Work supported by NSF grants CCR-9522092 and MIP-9630870, by NASA grant NAS1-19858, by ONR grants N00014-95-1-0779 and N00014-97-1-0562 and by ARC grant 04/15/412/194.