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An efficient implementation method of fractal image compression on dynamically reconfigurable architecture

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Parallel and Distributed Processing (IPPS 1999)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1586))

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Abstract

This paper proposes a method for implementing fractal image compression on dynamically reconfigurable architecture. In the encoding of this compression, metric computations among image blocks are the most time consuming. In our method, processing elements (PEs) configured for each image block perform these computations in a pipeline manner. By configuring PEs, we can reduce the number of adders, which are the main computing elements, by half even in the worst case. This reduction increases the number of PEs that work in parallel. In addition, dynamic reconfigurability of hardware is employed to omit useless metric computations. Experimental results show that the resources for implementing the PEs are reduced to 60 to 70% and the omission of useless metric computations reduces the encoding time to 10 to 55%.

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José Rolim Frank Mueller Albert Y. Zomaya Fikret Ercal Stephan Olariu Binoy Ravindran Jan Gustafsson Hiroaki Takada Ron Olsson Laxmikant V. Kale Pete Beckman Matthew Haines Hossam ElGindy Denis Caromel Serge Chaumette Geoffrey Fox Yi Pan Keqin Li Tao Yang G. Chiola G. Conte L. V. Mancini Domenique Méry Beverly Sanders Devesh Bhatt Viktor Prasanna

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© 1999 Springer-Verlag

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Nagano, H., Matsuura, A., Nagoya, A. (1999). An efficient implementation method of fractal image compression on dynamically reconfigurable architecture. In: Rolim, J., et al. Parallel and Distributed Processing. IPPS 1999. Lecture Notes in Computer Science, vol 1586. Springer, Berlin, Heidelberg . https://doi.org/10.1007/BFb0097952

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  • DOI: https://doi.org/10.1007/BFb0097952

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-65831-3

  • Online ISBN: 978-3-540-48932-0

  • eBook Packages: Springer Book Archive

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