The re-configurable delay-insensitive Flysig architecture

Abstract

This article describes a new re-configurable architecture design suitable for high performance signal processing applications. The main benefits beside re-configurability are high computation performance, robustness against technology changes, and short design time. Therefore four design paradigms are combined: re-configurable functionality, data-flow orientation, delayinsensitive implementation, and pipelined bit-serial operators. Based on this paradigms a re-configurable high performance processor for cyclic execution of real-time critical algorithms, i.e. a specialized application domain has been designed. Comparable to FPGA based designs operators and interconnections are configurable. In contrast to FPGAs the basic configurable parts are much more complex. This ensures feasibility of complex designs and high complexity The implementation follows a bottom up approach while the concept has been specified top-down.

dataFLow oriented delaY-insensitive SIGnal processing