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International Parallel Processing Symposium

IPPS 1999: Parallel and Distributed Processing pp 712–715Cite as

FPGA implementation of modular exponentiation

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1586))

Abstract

An efficient implementations of the main building block in the RSA cryptographic scheme is achieved by mapping a bit-level systolic array for modular exponentiation onto Xilinx FPGAs. One XC6000 chip, or 4 Kgates accommodates 132-bit long integers. 16 Kgates is required for modular exponentiation of 512 bit keys, with the estimated bit rate 800 Kb/sec.

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References

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Author information

Authors and Affiliations

  1. Institute of Mathematics, National Academy of Sciences of Belarus, 11 Surganova st, 220072, Minsk, Belarus

    Alexander Tiountchik

  2. Advanced Computing Research Centre, University of South Australia, 5095, Mawson Lakes, SA, Australia

    Elena Trichina

Authors
  1. Alexander Tiountchik
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  2. Elena Trichina
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Editor information

José Rolim Frank Mueller Albert Y. Zomaya Fikret Ercal Stephan Olariu Binoy Ravindran Jan Gustafsson Hiroaki Takada Ron Olsson Laxmikant V. Kale Pete Beckman Matthew Haines Hossam ElGindy Denis Caromel Serge Chaumette Geoffrey Fox Yi Pan Keqin Li Tao Yang G. Chiola G. Conte L. V. Mancini Domenique Méry Beverly Sanders Devesh Bhatt Viktor Prasanna

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© 1999 Springer-Verlag

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Tiountchik, A., Trichina, E. (1999). FPGA implementation of modular exponentiation. In: Rolim, J., et al. Parallel and Distributed Processing. IPPS 1999. Lecture Notes in Computer Science, vol 1586. Springer, Berlin, Heidelberg . https://doi.org/10.1007/BFb0097960

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  • DOI: https://doi.org/10.1007/BFb0097960

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-65831-3

  • Online ISBN: 978-3-540-48932-0

  • eBook Packages: Springer Book Archive

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