Abstract
This paper investigates efficient hardware architectures for implementation of 1-D and 2-D discrete wavelet transforms (DWTs). The architectures are based on the lifting scheme. We propose a general structure to minimize the number of multipliers and adders for 1-D DWTs. Compared to previous conventional architectures, the architecture presented here is more efficient in terms of the required arithmetic units. Moreover, we describe a new frame scan method for a block-based 2-D DWT structure which provides a flexible trade-off between the required internal memory size and external memory access. In contrast, other 2-D DWT structures require a fixed memory size.
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Salehi, S.A., Sadri, S. Investigation of Lifting-Based Hardware Architectures for Discrete Wavelet Transform. Circuits Syst Signal Process 28, 1–16 (2009). https://doi.org/10.1007/s00034-008-9068-1
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DOI: https://doi.org/10.1007/s00034-008-9068-1