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The Combinational and Sequential Adiabatic Circuit Design and Its Applications

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Abstract

In this paper, a new design of adiabatic circuit, called the quasi-static efficient charge recovery logic (QSECRL) is proposed. To achieve minimum energy consumption, this paper proposes a technique to reduce channel resistance and remove diodes from the signal path. This design method can be implemented in both combination logic and sequential logic. The counter circuit and the 8-bit carry look-ahead (CLA) circuit, a more complex circuit, are selected to evaluate this proposed design. All simulations in this paper have been implemented by SPICE with the 0.8 μm MOSIS technology MOS transistor model under 2-volt (peak-peak) sinusoidal power-clock supply. The results show significantly improved performance of the 8-bit CLA circuit with 20–30 fJ and 70 fJ energy consumption at 10–100 MHz and 500 MHz operating frequency, respectively.

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Abbreviations

V d :

Voltage drop in diode

V φ :

Peak-peak voltage of power-clock supply (φ)

V CL :

Voltage drop in capacitive load

V th :

MOS transistor threshold voltage

R ch :

MOS transistor channel resistance

C L :

Capacitive load

T :

Period of power-clock supply

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  1. Department of Telecommunication Engineering, Faculty of Engineering, King Mongkut’s Institute of Technology Ladkrabang, Bangkok, 10520, Thailand

    Sompong Wisetphanichkij & Kobchai Dejhan

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  1. Sompong Wisetphanichkij
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  2. Kobchai Dejhan
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Correspondence to Sompong Wisetphanichkij.

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Wisetphanichkij, S., Dejhan, K. The Combinational and Sequential Adiabatic Circuit Design and Its Applications. Circuits Syst Signal Process 28, 523–534 (2009). https://doi.org/10.1007/s00034-009-9096-5

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  • DOI: https://doi.org/10.1007/s00034-009-9096-5

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