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AC-Boosting Frequency Compensation with Double Pole-Zero Cancellation for Multistage Amplifiers

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Abstract

In this paper, we present an AC-boosting compensation topology with double pole-zero cancellation (ACBC-DPZ) for a multistage amplifier driving a very large capacitive load. The proposed technique modifies the original AC-boosting compensation (ACBC) topology to increase the power-bandwidth efficiency and reduce the size for the output power transistor and compensation capacitor. Simulation results show that the ACBC-DPZ amplifier using a CSM 0.18 μm CMOS process can achieve a unity gain bandwidth of 14 MHz and an average slew rate of 3.88 V/μs at 1500 pF load. The amplifier dissipates 2.55 mW at a 1.8 V supply.

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Authors and Affiliations

  1. School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, Singapore

    M. T. Tan, P. K. Chan, C. K. Lam & C. W. Ng

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  1. M. T. Tan
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  2. P. K. Chan
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  3. C. K. Lam
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  4. C. W. Ng
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Correspondence to P. K. Chan.

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Tan, M.T., Chan, P.K., Lam, C.K. et al. AC-Boosting Frequency Compensation with Double Pole-Zero Cancellation for Multistage Amplifiers. Circuits Syst Signal Process 29, 941–951 (2010). https://doi.org/10.1007/s00034-010-9180-x

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  • DOI: https://doi.org/10.1007/s00034-010-9180-x

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