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CMOS Readout Circuit with New Background Suppression Technique for Room-Temperature Infrared FPA Applications

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Abstract

A high-performance CMOS readout integrated circuit (ROIC) with a new temperature and power supply independent background current and dark current suppression technique for room-temperature infrared focal plane array applications is proposed. The structure is composed of an improved switched current integration stage, a new current-mode background suppression circuit, and a high linearity, high voltage swing output stage. An experimental readout chip has been designed and fabricated using the Chartered 0.35 μm CMOS process. Both the function and performance of the proposed readout circuit have been verified by experimental results. The test results show that the detector bias error in this structure is less than 0.1 mV. The input resistance is close to an ideal value of zero, and the injection efficiency is almost 100%. The output voltage linearity of the designed circuit is more than 99%. The background suppression level is tunable between 8 nA–1.5 μA, and the background suppression uniformity is as high as 100%. A unit-cell occupies a 10 μm × 15 μm area and consumes less than 0.07 mW power.

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Authors and Affiliations

  1. Tianjin University ASIC Design Center, School of Electronic Information and Engineering, Tianjin University, Tianjin, 300072, China

    X. Y. Li, S. Y. Yao & Y. Q. Zhao

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  1. X. Y. Li
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  2. S. Y. Yao
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  3. Y. Q. Zhao
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Correspondence to X. Y. Li.

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Li, X.Y., Yao, S.Y. & Zhao, Y.Q. CMOS Readout Circuit with New Background Suppression Technique for Room-Temperature Infrared FPA Applications. Circuits Syst Signal Process 29, 1027–1040 (2010). https://doi.org/10.1007/s00034-010-9197-1

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  • DOI: https://doi.org/10.1007/s00034-010-9197-1

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