Abstract
This paper presents a VLSI implementation of a novel hybrid architecture that computes three 8-point 1-D transforms—the discrete cosine transform, the discrete Fourier transform, and the Haar wavelet transform—on a single chip. The architecture is developed on matrix factorization and row permutation algorithms, where the basis forward transformation matrices are decomposed into common submatrices which are then shared among the transforms. A two-level hardware mapping has been employed which is parallel, pipelined, and multiplexed. The hybrid architecture, the first of its kind, is implemented using 0.18 μm CMOS technology. The estimated die size of the hybrid processor is 0.203 sq. mm, the frequency of operation is 100 MHz, the gate count is 20,400, and the power consumption is 15.38 mW. Compared to the existing designs, the proposed hybrid scheme has less power density and higher frequency of operation, making it very suitable for modern multimedia-based transcoding applications.
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Wahid, K.A., Islam, M.A., Shimu, S.S. et al. Hybrid Architecture and VLSI Implementation of the Cosine–Fourier–Haar Transforms. Circuits Syst Signal Process 29, 1193–1205 (2010). https://doi.org/10.1007/s00034-010-9200-x
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DOI: https://doi.org/10.1007/s00034-010-9200-x