Abstract
A new current-mode analog computational circuit is presented. The circuit can be digitally controlled to produce multiplying, squaring and inverse functions. The design is based on using MOSFETs operating in sub-threshold region to achieve ultra low power dissipation. The circuit is operated from a ±0.75 V DC supply. The proposed circuit has been simulated using Tanner in 0.35-μm TSMC CMOS process. Simulation results confirm the functionality of the circuit. The total power consumption is 2.3 μW, total harmonic distortion is 1.1 %, maximum linearity error is 0.3 % and the bandwidth is 2.3 MHz.












Similar content being viewed by others
References
A. Boura, M. Husak, nMOS and pMOS translinear multiplying cell for current-mode signal processing, in Proceedings of the Seventh International Conference on Advanced Semiconductor Devices and Microsystems (2008), pp. 83–86
C.-C. Chang, S.I. Liu, Weak inversion four-quadrant multiplier and two-quadrant divider. Electron. Lett. 34(22), 2079–2080 (1998)
D. Coue, G. Wilson, A four-quadrant subthreshold mode multiplier for analog neural network applications. IEEE Trans. Neural Netw. 7(5), 1212–1219 (1996)
Z. Dong, P.E. Allen, Low-voltage, supply independent CMOS bias current, in Proceedings of the 45th Midwest Symposium on Circuits and System (2002), pp. 568–570
C.C. Enz, F. Krummenacher, E.A. Vittoz, An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications. Analog Integr. Circuits Signal Process. 8, 83–114 (1995)
M. Gravati, M. Valle, G. Ferri, N. Guerrine, L. Reyes, A novel current-mode very low power analog CMOS four-quadrant multiplier, in Proceedings of ESSCIRC, France (2005), pp. 495–498
W. Liu, S.I. Liu, Design of a CMOS low-power and low-voltage four-quadrant analog multiplier. Analog Integr. Circuits Signal Process. 63(2), 307–312 (2010)
A. Panigrahi, Design of four-quadrant analog CMOS multiplier in subthreshold region. Eur. J. Sci. Res. 50(3), 289–299 (2011)
C.P. Raj, S.L. Pinjare, Design and analog VSLI implementation of NeuralNetwork. Eur. J. Sci. Res. 27(2), 199–216 (2009)
Acknowledgements
The authors would like to thank King Abdulaziz City for Science and Technology for financial support under NSTIP funded Project No. 09-ELE782-04 and KFUPM for using all facilities to carry out this research.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Al-Absi, M.A., Hussein, A. & TaherAbuelma’atti, M. A Low Voltage and Low Power Current-Mode Analog Computational Circuit. Circuits Syst Signal Process 32, 321–331 (2013). https://doi.org/10.1007/s00034-012-9446-6
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00034-012-9446-6