Abstract
A general purpose Conic Section Function Neural Network (CSFNN) circuitry in Very Large Scale Integration (VLSI) has been designed for an object recognition application. CSFNN is capable of making open and closed decision regions by combining the propagation rules of Radial Basis Functions (RBF) and Multilayer Perceptrons (MLP) on a single neural network with a unique propagation rule. Chip-in-the-loop learning technique was used during the training process. Utilizing mixed-mode hardware techniques, the inputs of the network and the feedforward signals are all analog while the control unit and storage of the network parameters are fully digital. CSFNN circuitry architecture is problem independent and consists of 16 inputs, 16 hidden layer neurons and 8 outputs. Inheriting the merits of CSFNN, the circuitry has good recognition performance on several objects with invariance to pose, lighting, and brightness. The designed hardware achieved a good recognition performance by means of both accuracy and computational time comparable to CSFNN software.

















Similar content being viewed by others
References
J. Baker, CMOS Circuit Design, Layout, and Simulation, 2nd edn. (Wiley/IEEE Press, New York, 1997)
S. Bibyk, M. Ismail, T. Borgstrom, K. Adkins, R. Kaul, N. Khachab, S. Dupuie, Current-mode neural network building blocks for analog MOS VLSI, in IEEE Int. Symp. on Circuits and Systems, vol. 4 (1990), pp. 3283–3285
G.M. Bo, D.D. Caviglia, M. Valle, A current mode CMOS multi-layer perceptron chip, in Proc. of 5th Int. Conf. on Microelectronics for Neural Networks (1996), pp. 103–106
G. Cairns, L. Tarassenko, Learning with analogue VLSI MLPs, in Proc. of the 4th Int. Conf. on Microelectronics for Neural Networks and Fuzzy Systems (1994), pp. 67–76
G. Cauwenberghs, M.A. Bayoumi, Learning on Silicon Adaptive VLSI Neural Systems (Kluwer Academic, Norwell, 1999)
J. Chen, T. Shibata, A neuron-MOS-based VLSI implementation of pulse-coupled neural networks for image feature generation. IEEE Trans. Circuits Syst. I, Regul. Pap. 57, 1143–1153 (2010)
W. Chung-Yu, C. Chiu-Hung, A learnable cellular neural network structure with ratio memory for image processing. IEEE Trans. Circuits Syst. I, Fundam. Theory Appl. 49, 1713–1723 (2002)
S. Cohen, N. Intrator, Automatic model selection in a hybrid perceptron/radial network, in Multiple Classifier Systems. Lecture Notes in Computer Science, vol. 2096 (2001), pp. 440–454
G. Dorffner, Unified frameworks for MLP and RBFNs: introducing conic section function networks. Cybern. Syst. 25, 511–554 (1994)
B. Erkmen, T. Yildirim, Obtaining decision boundaries of CSFNN neurons using current mode analog circuitry, in Proc. of the 18th European Conf. on Circuit Theory and Design (2007), pp. 807–810
B. Erkmen, Mixed mode hardware realization of a general purposed artificial neural network. Ph.D. Thesis, Yildiz Technical University, Turkey (2007)
B. Erkmen, N. Kahraman, R.A. Vural, T. Yildirim, Conic section function neural network circuitry for offline signature recognition. IEEE Trans. Neural Netw. 21(4), 667–672 (2010)
H. Esmaelzadeh, C. Farshbaf, S.M. Lucas, S.M. Fakhraie, Digital implementation for conic section function networks, in Proc. of the 16th Int. Conf. on Microelectronics (2004), pp. 564–567
S. Haykin, Neural Networks. A Comprehensive Foundation (Macmillan, New York, 1994), pp. 363–370
D.F. Hoeschele, Analog-to-Digital and Digital-to-Analog Conversion Techniques, 2nd edn. (Wiley, New York, 1994)
J.-Y. Kim et al., A 201.4 GOPS 496 mW real-time multi-object recognition processor with bio-inspired neural perception engine. IEEE J. Solid-State Circuits 45(1), 32–45 (2010)
K.J. Kyoung, Fully-pipelining hardware implementation of neural network for text-based images retrieval, in Lecture Notes in Computer Science, vol. 3973 (2006), pp. 1350–1356
Y. Lecun, F.J. Huang, L. Bottou, Learning methods for generic object recognition with invariance to pose and lighting, in Proc. of the Computer Vision and Pattern Recognition Conference, vol. 2 (2004), pp. 97–104
G. Lowe, Distinctive image features from scale-invariant keypoints. Int. J. Comput. Vis. 60, 91–110 (2004)
C. Lu, B. Shi, L. Chen, A programmable on-chip BP learning neural network with enhanced neuron characteristics, in IEEE Int. Symp. on Circuits and Systems, May 2001, vol. 3 (2001), pp. 573–576
P. Masa, K. Hoen, H. Wallinga, 70 input, 20 nanosecond pattern classifier, in IEEE Int. Conf. on Neural Networks (1994), pp. 1854–1859
M. Mirhassani, M. Ahmadi, W.C. Miller, A mixed-signal VLSI neural network with on-chip learning, in Canadian Conf. on Electrical and Computer Engineering (2003), pp. 1–4
M. Mirhassani, M. Ahmadi, W.C. Miller, A feed-forward time-multiplexed neural network with mixed-signal neuron-synapse arrays, in The Microelectronic Engineering Journal, vol. 84 (2007), pp. 300–307. Special issue on VLSI Design and Test
A.J. Montalvo, R.S. Gyurcsik, J.J. Paulos, Toward a general-purpose analog VLSI neural network with on-chip learning. IEEE Trans. Neural Netw. 8, 413–423 (1997)
P. Pavan, R. Bez, P. Olivo, E. Zanoni, Flash memory cells: an overview, in Proceedings of the IEEE, vol. 85 (1997), pp. 1248–1271
A. Schmid, Y. Leblebici, D. Mlynek, Mixed analogue-digital artificial-neural-network architecture with on-chip learning, in IEE Proc. on Circuits, Devices and Systems, vol. 146 (1999), pp. 345–349
A.K. Sharma, Advanced Semiconductor Memories, Architectures and Applications (Wiley-Interscience/IEEE Press, Norwell, 2003)
B.J. Sheu, J. Choi, Neural Information Processing and VLSI (Kluwer Academic, New York, 1995), pp. 3–16
F. Stupmann, S. Rode, G. Geske, Single chip-VLSI-realization of a neural net for image recognition, in IEEE Int. Conf. on Industrial Technology, vol. 2 (2002), pp. 1345–1348
R.A. Vural, N. Kahraman, B. Erkmen, T. Yildirim, Object recognition on general purposed conic section function neural network integrated circuit, in 16th IEEE Signal Processing, Communication and Applications Conference (2008), pp. 1–4
S. Wolpert, L.A. Lee, J.F. Heisler, Circuits for a VLSI-based standalone backpropagation neural network, in Proc. of the IEEE Bioengineering Conference Northeast (1992), pp. 47–48
M.P. Yang, Implementation of an RBF neural network on embedded systems: real-time face tracking and identity verification. IEEE Trans. Neural Netw. 14, 1162–1175 (2003)
T. Yıldırım, J.S. Marsland, An RBF/MLP hybrid neural network implemented in VLSI hardware, in Proc. 8th Int. Conf. on Neural Networks and Their Applications (1995), pp. 156–160
Acknowledgement
This work was supported by the TUBITAK—The Scientific and Technological Research Council of Turkey. Project Number: 104E133.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Erkmen, B., Vural, R.A., Kahraman, N. et al. A Mixed Mode Neural Network Circuitry for Object Recognition Application. Circuits Syst Signal Process 32, 29–46 (2013). https://doi.org/10.1007/s00034-012-9458-2
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00034-012-9458-2