Abstract
In mobile communication systems and multimedia applications, need for efficient reconfigurable digital finite impulse response (FIR) filters has been increasing tremendously because of the advantage of less area, low cost, low power and high speed of operation. This article presents a near optimum low- complexity, reconfigurable digital FIR filter architecture based on computation sharing multipliers (CSHM), constant shift method (CSM) and modified binary-based common sub-expression elimination (BCSE) method for different word-length filter coefficients. The CSHM identifies common computation steps and reuses them for different multiplications. The proposed reconfigurable FIR filter architecture reduces the adders cost and operates at high speed for low-complexity reconfigurable filtering applications such as channelization, channel equalization, matched filtering, pulse shaping, video convolution functions, signal preconditioning, and various other communication applications. The proposed architecture has been implemented and tested on a Virtex 2 xc2vp2-6fg256 field-programmable gate array (FPGA) with a precision of 8-bits, 12-bits, and 16-bits filter coefficients. The proposed novel reconfigurable FIR filter architecture using dynamically reconfigurable multiplier block offers good area and speed improvement compared to existing reconfigurable FIR filter implementations.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
K.H. Chen, T.D. Chiueh, A low-power digit-based reconfigurable FIR filter. IEEE Trans. Circuits Syst. II, Express Briefs 53(8), 617–621 (2006)
X. Chenghuan, C. He, Z. Shunan, W. Hua, Design and implementation of a high-speed programmable poly phase FIR filter, in Proc. 5th Int. Conf. Applicat.-Specific Integr. Circuit, vol. 2 (2003), pp. 783–787
S.S. Demirsoy, I. Kale, A.G. Dempster, Efficient implementation of digital filters using novel reconfigurable multiplier blocks, in Proceedings of Conference on Signals, Systems and Computers, vol. 1 (2004), pp. 461–464
R.I. Hartley, Sub-expression sharing in filters using canonic signed digit multipliers. IEEE Trans. Circuits Syst. II, Express Briefs 43(10), 677–688 (1996)
W. Jeong, K. Roy, C. Koh, High-performance low-power carry-select adder using dual transition skewed logic, in Proc. ESSCIRC (2001), pp. 172–175
J.-J. Lee, S.G. Yong, Implementation of a bit-level super-systolic FIR filter, in IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASlC2004)I, Aug. 4–5, 2004 (2004), pp. 206–209
R. Mahesh, A.P. Vinod, A new common sub-expression elimination algorithm for implementing low complexity FIR filters in software defined radio receivers, in Proc. IEEE Int Symp. on Circuits and Systems, Greece (2006), pp. 4515–4518
R. Mahesh, A.P. Vinod, A new common sub-expression elimination algorithm for realizing low complexity higher order digital filters. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 27(2), 217–219 (2008)
R. Mahesh, A.P. Vinod, New reconfigurable architectures for implementing FIR filters with low complexity. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 29(2), 275–288 (2010)
J.L. Mazher Iqbal, S. Varadarajan, High performance reconfigurable balanced shared memory architecture for embedded DSP. Int. J. Comput. Sci. Inf. Sec. 8(4), 198–206 (2010)
P.K. Meher, New approach to look-up-table design and memory-based realization of FIR digital filter. IEEE Trans. Circuits Syst. I, Regul. Pap. 57(3), 592–603 (2010)
P.K. Meher, A. Amira, FPGA realization of FIR filters by efficient and flexible systolization using distributed arithmetic. IEEE Trans. Signal Process. 56(7), 3009–3017 (2008)
K. Muhammad, K. Roy, Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling. IEEE Trans. Very Large Scale Integr. Syst. 10(3), 292–300 (2002)
J. Park, W. Jeong, H. Mahmoodi Meimand, Y. Wang, H. Choo, K. Roy, Computation sharing programmable FIR filter for low-power and high-performance applications. IEEE J. Solid-State Circuits 39(2), 348–357 (2004)
R. Pasko, P. Schaumont, V. Derudder, S. Vernalde, D. Durackova, A new algorithm for elimination of common sub-expressions. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 18(1), 58–68 (1999)
M.M. Peiro, E.I. Boemo, L. Wanhammar, Design of high-speed multiplier-less filters using a nonrecursive signed common sub-expression algorithm. IEEE Trans. Circuits Syst. II, Express Briefs 49(3), 196–203 (2002)
P. Tummeltshammer, J.C. Hoe, M. Puschel, Multiplexed multiple constant multiplication. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. 26(9), 1551–1563 (2007)
A.P. Vinod, E. Lai, Low power and high-speed implementation of FIR filters for software defined radio receivers. IEEE Trans. Wirel. Commun. 5(7), 1669–1675 (2006)
H. Yoo, D.V. Anderson, Hardware-efficient distributed arithmetic architecture for high-order digital filters, in Proc. IEEE Int. Conf. Acoustics, Speech, Signal Processing (ICASSP), vol. 5 (2005), pp. v/125–v/128
Y.J. Yu, Y.C. Lim, Optimization of linear phase FIR filters in dynamically expanding sub-expression space. Circuits Syst. Signal Process 29, 65–80 (2010)
T. Zhangwen, J. Zhang, H. Min, A high-speed, programmable, CSD coefficient FIR filter. IEEE Trans. Consum. Electron. 48(4), 834–837 (2002)
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Mazher Iqbal, J.L., Varadarajan, S. High Performance Reconfigurable FIR Filter Architecture Using Optimized Multiplier. Circuits Syst Signal Process 32, 663–682 (2013). https://doi.org/10.1007/s00034-012-9473-3
Received:
Revised:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00034-012-9473-3