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Low-voltage reduced complexity cells for MOS translinear loops

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Abstract

A novel bias scheme for realizing low-voltage second-order translinear loops is introduced in this paper. The provided design examples include current geometric-mean, squarer/divider, and multiplier/divider cells. The performed comparison shows that the derived analog signal processing blocks offer reduced circuit complexity and improved performance, compared with the corresponding already published counterparts.

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Authors and Affiliations

  1. Electronics Laboratory, Physics Department, University of Patras, 26504, Rio Patras, Greece

    C. Psychalinos & C. Laoudias

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  1. C. Psychalinos
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  2. C. Laoudias
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Correspondence to C. Psychalinos.

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Psychalinos, C., Laoudias, C. Low-voltage reduced complexity cells for MOS translinear loops. Circuits Syst Signal Process 32, 2445–2456 (2013). https://doi.org/10.1007/s00034-013-9567-6

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  • DOI: https://doi.org/10.1007/s00034-013-9567-6

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