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A Modified CORDIC FPGA Implementation for Wave Generation

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Abstract

This paper presents a modified coordinate rotation digital computer (CORDIC) algorithm implemented in parallel architecture to generate sine and cosine waveform. Since CORDIC is a combination of only additions and shifts, it can be efficiently implemented in hardware. The proposed algorithm further approximates the way of computing rotation angle based on Taylor series in order to reduce the usage of Read-Only-Memory (ROM) table. Thus area and power is reduced due to partial usage of ROM storage. The precision remains the same as the original algorithm. The modified 32-bits pipeline CORDIC are implemented in Spartan XC3S500E device using Xilinx ISE 12.3 design suite. The result is compared with original CORDIC and Xilinx coregen in device utilization. It is shown that the logic usage is 31 FFs and 285 FFs less than the original design and Xilinx core, respectively. When compared with the original design, the signal power and total power reduction at 40 MHz clocks are 7.69 % and 1.35 %, respectively. The bit error remains at 10−8 dB level. The SNR of modified CORDIC is about 2 dB lower, which is acceptable in wave generation.

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References

  1. S. Aggarwal, P.K. Meher, K. Khare, Scale-free hyperbolic CORDIC processor and its application to waveform generation. IEEE Trans. Circuits Syst. I, Regular Pap. 60(2), 314–326 (2012)

    Article  MathSciNet  Google Scholar 

  2. C.Y. Chen, Reduced ROM-based architecture for sine/cosine generator. IET Signal Process. 2(2), 118–124 (2008)

    Article  MathSciNet  Google Scholar 

  3. D. De Caro, N. Petra, A.G.M. Strollo, Digital synthesizer/mixer with hybrid CORDIC-multiplier architecture: error analysis and optimization. IEEE Trans. Circuits Syst. I, Regul. Pap. 56(2), 364–373 (2009)

    Article  MathSciNet  Google Scholar 

  4. E. Deprettere, P. Dewilde, R. Udo, Pipelined CORDIC architectures for fast VLSI filtering and array processing, in IEEE International Conference on Acoustics, Speech, and Signal Processing, vol. 9 (1984), pp. 250–253

    Google Scholar 

  5. Y.H. Hu, S. Naganathan, An angle recoding method for CORDIC algorithm implementation. IEEE Trans. Comput. 42(1), 99–102 (1993)

    Article  Google Scholar 

  6. C. Mazenc, X. Merrheim, Computing functions arccos and arcsin using CORDIC. IEEE Trans. Comput. 42, 118–122 (1993)

    Article  Google Scholar 

  7. P.K. Meher, S.Y. Park, CORDIC designs for fixed angle of rotation. IEEE Trans. VLSI Syst. (2013)

  8. P. Pirsh, Architectures for Digital Signal Processing (Wiley, New York, 1998)

    Google Scholar 

  9. J.-L. Sanchez-Romero et al., Function approximation on decimal operands. Department of Computer Technology, University of Alicante, Spain

  10. T. Srikanthan, B. Gisuthan, Optimizing scaling factor computations in flat CORDIC. J. Circuits Syst. Comput. 11(1), 17–33 (2002)

    Google Scholar 

  11. L. Vachhani, K. Sridharan, P.K. Meher, Efficient CORDIC algorithms and architectures for low area and high throughput implementation. IEEE Trans. Circuits Syst. II, Express Briefs 56(1), 61–65 (2009)

    Article  Google Scholar 

  12. J. Valls, M. Kuhlmann, K.K. Parhi, Evaluation of CORDIC algorithms for FPGA design. J. VLSI Signal Process. Syst. Signal Image Video Technol. 32(3), 207–222 (2002)

    Article  MATH  Google Scholar 

  13. J.E. Volder, The CORDIC trigonometric computer technique. IRE Trans. Electron. Comput. 8(3), 330–334 (1959)

    Article  Google Scholar 

  14. J.S. Wather, A unified algorithm for elementary functions, in AFIPS Spring Joint Computer Conference (1971) pp. 379–385

    Google Scholar 

  15. C.l. Yu, A.Y. Wu, A cost-effective time-recursive FFT architecture based on improvement vector rotator for DMT transmitter. Department of Electrical Engineering, National Central University, Taiwan, ROC

  16. Z. Zhu, Y. Liu, Z. Jin, A low-power digital processing circuit for capacitive accelerometer. Proc. Inst. Mech. Eng., Part N, J. Nanoeng. Nanosyst. 227(2), 51–55 (2013)

    Google Scholar 

  17. http://www.xilinx.com/products/intellectual-property/CORDIC.htm

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Acknowledgements

This work is supported by the Fundamental Research Funds for the Central Universities (2012QNA4021) and the Zhejiang Natural Science Foundation under grant Q13F040001.

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Authors and Affiliations

  1. Microsat Research Center, Zhejiang University, Hangzhou, 310027, China

    Yidong Liu, Lihang Fan & Tieying Ma

  2. School of Optic and Electronic Technology, China Jiliang University, Hangzhou, 310018, China

    Tieying Ma

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  1. Yidong Liu
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  2. Lihang Fan
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  3. Tieying Ma
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Correspondence to Yidong Liu.

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Liu, Y., Fan, L. & Ma, T. A Modified CORDIC FPGA Implementation for Wave Generation. Circuits Syst Signal Process 33, 321–329 (2014). https://doi.org/10.1007/s00034-013-9638-8

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  • DOI: https://doi.org/10.1007/s00034-013-9638-8

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