Abstract
A simplified DFT-based algorithm and its VLSI implementation for accurate frequency estimation of single-tone complex sinusoid signal are investigated. The proposed algorithm estimates frequency by interpolation using Fourier coefficients. It consists of a coarse search followed by a fine search, and its performance closely achieves the Cramer–Rao low bound (CRLB) even in low SNR region. Moreover, a pipelined triple-mode CORDIC architecture is designed to efficiently support complex multiplication, complex magnitude calculation and real division. The triple-mode CORDIC-based radix-4 architecture is employed for the hardware implementation of the frequency estimator, and is suitable for not only fast Fourier transformation but also accurate frequency estimation. A frequency estimator with 1024-point samples is implemented and verified on FPGA. It works at 215 MHz on a Xilinx XC6VLX240T FPGA device, and uses up 4,161 registers and 6,986 slice LUTs. ASIC synthesis results show that it requires an area of 60K equivalent NAND2 gates with a clock rate of 500 MHz at SMIC 0.18 μm technology. The whole latency of the frequency estimator is 2336 cycles. The proposed architecture provides a good trade off between hardware overhead, estimation performance and computation latency.








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Acknowledgements
The authors would like to thank the editors and anonymous reviewers for providing valuable comments which helped in improving the manuscript. This work is supported by the National Natural Science Foundation of China, under Grant No. 60970037.
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Liu, D., Liu, H., Zhou, L. et al. Computationally Efficient Architecture for Accurate Frequency Estimation with Fourier Interpolation. Circuits Syst Signal Process 33, 781–797 (2014). https://doi.org/10.1007/s00034-013-9660-x
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DOI: https://doi.org/10.1007/s00034-013-9660-x