Method for Designing Efficient Mixed Radix Multipliers

Abstract

The multiplication of two signed inputs, $A {\times } B$, can be accelerated by using the iterative Booth algorithm. Although high radix multipliers require summing a smaller number of partial products, and consume less power, its performance is restricted by the generation of the required hard multiples of B ($\pm \phi B$ terms). Mixed radix architectures are presented herein as a method to exploit the use of several radices. In order to implement efficient multipliers, we propose to overlap the computation of the $\pm \phi B$ terms for higher radices with the addition of the partial products associated to lower radices. Two approaches are presented which have different advantages, namely a combinatory design and a synchronous design. The best solutions for the combinatory mixed radix multiplier for $64\times 64$ bits require $8.78$ and $6.55~\%$ less area and delay in comparison to its counterpart radix-4 multiplier, whereas the synchronous solution for $64\times 64$ bits is almost $4{\times }$ smaller in comparison with the combinatory solution, although at the cost of about $5.3{\times }$ slowdown. Moreover, we propose to extend this technique to further improve the multipliers for residue number systems. Experimental results demonstrate that best proposed modulo $2^{n}{-}1$ and $2^{n}{+}1$ multiplier designs for the same width, $64{\times }64$ bits, provide an Area-Delay-Product similar for the case of the combinatory approach and $20~\%$ reduction for the synchronous design, when compared to their respective counterpart radix-4 solutions.