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Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers

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Abstract

Partial product generation (PPG), in radix-10 multiplication hardware, is often done through selection of pre-computed decimal multiples of the multiplicand. However, ASIC and FPGA realization of classical PPG via digit-by-digit multiplication has recently attracted some researchers. For example, a sequential multiplier, squarer, divider, FPGA parallel multiplier, and array multiplier are all based on a specific binary-coded decimal (BCD) digit multiplier (BDM). Most BDMs, as we have encountered, compute the binary product of two 1-digit BCD operands, and convert it to 2-digit BCD product. We provide our own version of two of these works with some adjustments and improvements, and offer two new low-cost BDMs in this category. However, a recent FPGA BDM uses straightforward truth table approach from scratch and skips binary product generation. We redesign the latter via low-level FPGA programming, and also provide its ASIC realization. We synthesize all the studied and new designs on ASIC and FPGA platforms, exhaustively check them for correctness, and compare their performance, to show that our two new designs, and the ASIC and new FPGA realizations of the aforementioned fully truth table-based design, outperform the previous ones in terms of one or more figures of merit.

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Authors and Affiliations

  1. Iranian Research Organization for Science and Technology (IROST), Tehran, Iran

    Saeid Gorgin

  2. Department of Electrical and Computer Engineering, Shahid Beheshti University, Tehran, Iran

    Ghassem Jaberipur & Reza Hashemi Asl

  3. School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran

    Saeid Gorgin & Ghassem Jaberipur

Authors
  1. Saeid Gorgin
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  2. Ghassem Jaberipur
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  3. Reza Hashemi Asl
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Correspondence to Ghassem Jaberipur.

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Gorgin, S., Jaberipur, G. & Hashemi Asl, R. Efficient ASIC and FPGA Implementation of Binary-Coded Decimal Digit Multipliers. Circuits Syst Signal Process 33, 3883–3899 (2014). https://doi.org/10.1007/s00034-014-9823-4

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  • DOI: https://doi.org/10.1007/s00034-014-9823-4

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