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Current-Mode Winner-Take-All Circuit with Improved Dynamic Response

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Abstract

A novel current-mode Winner-Take-All (WTA) topology is presented in this paper. The dynamic response of the circuit is improved by lowering the voltage swing required at the input nodes to turn on the winning cell. The WTA was designed and fabricated in 0.13 \(\upmu \)m CMOS technology with 2.5 V single supply voltage. Experimental results show an at least 26 % reduction in response time, as well as a reduction in the maximum output current error, when compared to other widely used current-mode topologies, with comparable bandwidth, area, and power consumption. The area of the proposed circuit is 47 \(\times \) 41 \(\upmu \mathrm{m}^{2}\) and it consumes 87 \(\upmu \)W per unit cell. The measured maximum output current error was 4.8 \(\upmu \)A, and a resolution of 1.85 \(\upmu \)A was obtained. The capability of the WTA to rectify signals was also experimentally demonstrated.

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Acknowledgments

This work was supported by CONACyT 227989 Doctoral Grant and CONACyT CB-SEP-2008-01-99901 Research Project.

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Authors and Affiliations

  1. Electronics Department, Instituto Nacional de Astrofísica, Óptica y Electrónica (INAOE), Luis Enrique Erro No.1, 72840, Tonantzintla (Puebla), Mexico

    David Moro-Frias, Carlos Ventura-Arizmendi & Maria-Teresa Sanz-Pascual

  2. Department of Electrical and Electronic Engineering, Universidad Pública de Navarra (UPNA), Campus de Arrosadía, 31006, Pamplona (Navarra), Spain

    Carlos-Aristoteles de la Cruz-Blas

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  1. David Moro-Frias
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  2. Carlos Ventura-Arizmendi
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  3. Maria-Teresa Sanz-Pascual
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  4. Carlos-Aristoteles de la Cruz-Blas
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Correspondence to Maria-Teresa Sanz-Pascual.

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Moro-Frias, D., Ventura-Arizmendi, C., Sanz-Pascual, MT. et al. Current-Mode Winner-Take-All Circuit with Improved Dynamic Response. Circuits Syst Signal Process 34, 625–639 (2015). https://doi.org/10.1007/s00034-014-9865-7

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