Skip to main content
SpringerLink
Log in

On the Case of Using Aggregated Page Programming for Future MLC NAND Flash Memory

  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

Multi-level per cell (MLC) technique has been widely used to improve the storage density of NAND flash memory. In current design practice, bits stored in one cell are mapped to different pages, and all pages are protected with the same error correction code (ECC). However, those bits in one MLC flash memory cell have different error rates, and such unbalance increases with the number of bits in one cell. To guarantee the storage integrity, ECC should be tuned to cover the worst case page, which results in over-protection and redundancy waste for other pages and hence reduces storage capacity. This bit-to-cell mapping scheme also limit the number of bits in one cell to be integer. This paper proposes an aggregated page programming scheme, which maps all bits in one cell into the same page, to balance all pages to experience the same but lower overall bit error rates, so that the weaker ECC with higher coding rate can be employed. Furthermore, the noise margin of NAND flash memory cell decreases with program/erase cycling. To exploit such noise margin dynamics, this paper proposes to accommodate more storage levels in one cell during its early lifetime and dynamically modulate the number of storage levels to increase the overall effective storage capacity. Not-a-power-of-2 storage levels in one cell should be used to exploit the storage capacity aggressively, which can be enabled through proposed aggregated page programming scheme. Simulation results show the program capacity can be increased by more than 50 %.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11

Similar content being viewed by others

References

  1. R. Bez, E. Camerlenghi, A. Modelli, A. Visconti, Introduction to flash memory. Proc. IEEE 91, 489–502 (2003)

    Article  Google Scholar 

  2. P. Cappelletti, R. Bez, D. Cantarelli, L. Fratin, Failure mechanisms of flash cell in program/erase cycling, in Proceedings of International Electron Devices Meeting (1994), pp. 291–294

  3. C. Compagnoni, M. Ghidotti, A. Lacaita, A. Spinelli, A. Visconti, Random telegraph noise effect on the programmed threshold-voltage distribution of flash memories. IEEE Electron Device Lett. 30(9), 984–986 (2009)

    Article  Google Scholar 

  4. C. Compagnoni, A. Spinelli, R. Gusmeroli, A. Lacaita, S. Beltrami, A. Ghetti, A. Visconti, First evidence for injection statistics accuracy limitations in nand flash constant-current fowler-nordheim programming, in Proceedings of IEEE International Electron Devices Meeting (2007), pp. 165–168

  5. C.M. Compagnoni, C. Miccoli, R. Mottadelli, S. Beltrami, M. Ghidotti, A.L. Lacaita, A.S. Spinelli, A. Visconti, Investigation of the threshold voltage instability after distributed cycling in nanoscale nand flash memory arrays, in Proceedings of IEEE International Reliability Physics Symposium (IRPS) (2010), pp. 604–610

  6. K. Fukuda, Y. Shimizu, K. Amemiya, M. Kamoshida, C. Hu, Random telegraph noise in flash memories model and technology scaling, in Proceedings of IEEE International Electron Devices Meeting (2007), pp. 169–172

  7. T. Futatsuyama, N. Fujita, N. Tokiwa, Y. Shindo, T. Edahiro, T. Kamei, H. Nasu, M. Iwai, K. Kato, Y. Fukuda, A 113mm\(^2\) 32 Gb 3b/cell NAND flash memory, in Proceedings of IEEE International Solid-State Circuits Conference (2009), pp. 242–243

  8. F. García-Herrero, M. Canet, J. Valls, Architecture of generalized bit-flipping decoding for high-rate non-binary LDPC codes. Circuits Syst. Signal Process. 32, 1–15 (2013)

    Article  Google Scholar 

  9. D. Guiqiang, L. Shu, Z. Tong, Using data postcompensation and predistortion to tolerate cell-to-cell interference in MLC NAND flash memory. IEEE Trans. Circuits Syst. Regul. Pap. 57(10), 2718–2728 (2010)

    Article  Google Scholar 

  10. T.S. Jung, Y.J. Choi, K.D. Suh, B.H. Suh, J.K. Kim, Y.H. Lim, Y.N. Koh, J.W. Park, K.J. Lee, J.H. Park, A 117-mm 3.3-V only 128-Mb multilevel NAND flash memory for mass storage applications. IEEE J. Solid-State Circuits 31(11), 1575–1583 (1996)

    Article  Google Scholar 

  11. K. Kim, Future memory technology: challenges and opportunities, in Proceedings of International Symposium on VLSI Technology, Systems and Applications (2008), pp. 5–9

  12. J. Lee, J. Choi, D. Park, K. Kim, R. Center, S. Co, S. Gyunggi-Do, Effects of interface trap generation and annihilation on the data retention characteristics of flash memory cells. IEEE Trans. Device Mater. Reliab. 4(1), 110–117 (2004)

    Article  Google Scholar 

  13. J.D. Lee, S.H. Hur, J.D. Choi, Effects of floating-gate interference on NAND flash memory cell operation. IEEE Electron. Device Lett. 23(5), 264–266 (2002)

    Article  Google Scholar 

  14. Y. Li, S. Lee, Y. Fong, F. Pan, T.C. Kuo, J. Park, T. Samaddar, H.T. Nguyen, M.L. Mui, K. Htoo, A 16 Gb 3-bit per cell (X3) NAND flash memory on 56 nm technology with 8 MB/s write rate. IEEE J. Solid-State Circuits 44, 195–207 (2009)

    Article  Google Scholar 

  15. H. Liu, S. Groothuis, C. Mouli, J. Li, K. Parat, T. Krishnamohan, 3D simulation study of cell–cell interference in advanced NAND flash memory, in Proceedings of IEEE Workshop on Microelectronics and Electron Devices (2009)

  16. G. Marotta, A. Macerola, A. D’Alessandro, A. Torsi, C. Cerafogli, C. Lattaro, C. Musilli, D. Rivers, E. Sirizotti, F. Paolini, A 3bit/cell 32GB nand flash memory at 34 nm with 6 mb/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13 MB/s, in Proceedings of IEEE International Solid-State Circuits Conference (2010), pp. 444–445

  17. N. Mielke, H. Belgal, A. Fazio, Q. Meng, N. Righos, Recovery effects in the distributed cycling of flash memories, in Proceedings of IEEE International Reliability Physics Symposium (2006), pp. 29–35

  18. N. Mielke, H. Belgal, I. Kalastirsky, P. Kalavade, A. Kurtz, Q. Meng, N. Righos, J. Wu, Flash eeprom threshold instabilities due to charge trapping during program/erase cycling. IEEE Trans. Device Mater. Reliab. 4(3), 335–344 (2004)

    Article  Google Scholar 

  19. S. Ogawa, N. Shiono, Generalized diffusion-reaction model for the low-field charge-buildup instability at the Si–SiO\(_{2}\) interface. Phys. Rev. B 51, 4218–4230 (1995)

    Article  Google Scholar 

  20. P. Olivo, B. Ricco, E. Sangiorgi, High-field-induced voltage-dependent oxide charge. Appl. Phys. Lett. 48, 1135 (1986)

    Article  Google Scholar 

  21. K.T. Park, M. Kang, D. Kim, S.W. Hwang, B.Y. Choi, Y.T. Lee, C. Kim, K. Kim, A zeroing cell-to-cell interference page architecture with temporary LSB storing and parallel MSB program scheme for MLC NAND flash memories. IEEE J. Solid-State Circuits 43, 919–928 (2008)

    Article  Google Scholar 

  22. K. Prall, Scaling non-volatile memory below 30 nm, in Proceedings of IEEE 2nd Non-Volatile Semiconductor Memory Workshop (2007), pp. 5–10

  23. W. Ryan, S. Lin, Channel Codes: Classical and Modern (Cambridge University Press, Cambridge, 2009)

    Book  Google Scholar 

  24. N. Shibata, H. Maejima, K. Isobe, K. Iwasa, M. Nakagawa, M. Fujiu, T. Shimizu, M. Honma, S. Hoshi, T. Kawaai, A 70 nm 16Gb 16-level-cell NAND flash memory. IEEE J. Solid-State Circuits 43, 929–937 (2008)

    Article  Google Scholar 

  25. K.D. Suh, B.H. Suh, Y.H. Lim, J.K. Kim, Y.J. Choi, Y.N. Koh, S.S. Lee, S.C. Kwon, B.S. Choi, J.S. Yum, A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme. IEEE J. Solid-State Circuits 30(11), 1149–1156 (1995)

    Article  Google Scholar 

  26. K. Takeuchi, T. Tanaka, H. Nakamura, A double-level-Vth select gate array architecture for multilevel NAND flash memories. IEEE J. Solid-State Circuits 31(4), 602–609 (1996)

    Article  Google Scholar 

  27. C. Trinh, N. Shibata, T. Nakano, M. Ogawa, J. Sato, Y. Takeyama, K. Isobe, B. Le, F. Moogat, N. Mokhlesi, A 5.6MB/s 64Gb 4b/cell NAND flash memory in 43nm CMOS, in Proceedings of IEEE International Solid-State Circuits Conference (2009), pp. 246–247

  28. D. Wellekens, J. Van Houdt, L. Faraone, G. Groeseneken, H. Maes, Write/erase degradation in source side injection flash eeprom’s: characterization techniques and wearout mechanisms. IEEE Trans. Electron Devices 42(11), 1992–1998 (1995)

    Article  Google Scholar 

  29. H. Yang, H. Kim, S.I. Park, J. Kim, S.H. Lee, J.K. Choi, D. Hwang, C. Kim, M. Park, K.H. Lee, Reliability issues and models of sub-90 nm nand flash memory cells, in Proceedings of International Conference on Solid-State and Integrated Circuit Technology (2006), pp. 760–762

  30. J.B. Yang, T.P. Chen, S.S. Tan, L. Chan, Analytical reaction–diffusion model and the modeling of nitrogen-enhanced negative bias temperature instability. Appl. Phys. Lett. 88, 172109 (2006)

    Article  Google Scholar 

Download references

Acknowledgments

This research was supported partly by the National Natural Science Foundation of China (No. 61231018).

Author information

Authors and Affiliations

  1. Xi’an Jiaotong University, Xi’an, 710049, Shaanxi, People’s Republic of China

    Wenzhe Zhao & Nanning Zheng

  2. Skyera Inc., 1704 Automation Pkwy, San Jose, CA, 95131, USA

    Guiqiang Dong

  3. Chongqing Communication Institute, Chongqing, 400035, People’s Republic of China

    Hui Han

  4. Rensselaer Polytechnic Institute, Troy, NY, 12180, USA

    Tong Zhang

Authors
  1. Wenzhe Zhao
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Guiqiang Dong
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Hui Han
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Nanning Zheng
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Tong Zhang
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Wenzhe Zhao.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Zhao, W., Dong, G., Han, H. et al. On the Case of Using Aggregated Page Programming for Future MLC NAND Flash Memory. Circuits Syst Signal Process 34, 557–577 (2015). https://doi.org/10.1007/s00034-014-9869-3

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-014-9869-3

Keywords

Search

Navigation