Abstract
Testing power dissipation of on-chip networks (NoC) is an interesting topic, which is still unexplored specially analytically. In this paper, a transistor level model is proposed to study the testing power and area of testing logic in a mesh NoC using IEEE 1149.1-based approach. For the purpose of verification, HSPICE simulation and FPGA implementation are used. The switching activities are computed using a special purpose cycle-accurate NoC simulator. At the end, the model is used to calculate test power and spot the most energy consuming and area occupying component of a typical NoC testing circuit.
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Appendix
Appendix
1.1 Multiplexer Energy (\(E_\mathrm{MUX}\))
Capacitances of a common N to 1 multiplexer can be modelled as follows. According to the sample transmission-gate-based 4 to 1 multiplexer shown in Fig. 11, the total capacitance is divided into four categories being total gate (\(C_\mathrm{gt}\)), junction (\(C_\mathrm{jn}\)), inverters on complement select inputs (\(C_\mathrm{inv}\)), and interconnection wire capacitances(\(C_\mathrm{w}\)). Therefore, the energy model for a generalised \(N\) to 1 multiplexer could be expressed as
The total gate capacitance times related switching activity is given as
The total junction capacitance times related switching activity is given as
where \(C_\mathrm{j_{n}}\) and \(C_\mathrm{j_{p}}\) are junction capacitances of NMOS and PMOS, respectively. The total inverters’ capacitance times related switching activities is given as
1.2 D-Latch and D Flip-Flop Energies (\(E_{D-Latch}\) and \(E_{DFF}\))
Similarly, the total energy of a D-latch module as illustrated in Fig. 12 can be modelled as
where \(\alpha _\mathrm{clk}\) and \(\alpha _{d}\) are the clock and D input switching activities, and \(inv3\) is the inverter to provide \(clkb\) signal. The \(C_\mathrm{inv}\) is defined as
In addition, according to Fig. 13, the energy of a master-slave DFF is expressed as
1.3 NAND Energy
A common CMOS energy is implemented according to Fig. 14 and its energy consumption is given as
where \(\alpha C_\mathrm{NAND}\) is expressed as
1.4 XOR Energy
A common CMOS energy is implemented according to Fig. 15 and its energy consumption is given as
where \(\alpha C_\mathrm{XOR}\) is given as
1.5 OR Energy
A common CMOS energy is implemented according to Fig. 16 and its energy consumption is given as
where \(\alpha C_\mathrm{OR}\) is given as
1.6 Wire Energy
where, \(\alpha \), \(W\), \(L\), and \(C\) are the switching activity, width, length, and the sheet capacitance of the wire respectively.
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Senejani, M.N., Ghadiry, M., Ooi, C.Y. et al. Built-in Self Test Power and Test Time Analysis in On-chip Networks. Circuits Syst Signal Process 34, 1057–1075 (2015). https://doi.org/10.1007/s00034-014-9892-4
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DOI: https://doi.org/10.1007/s00034-014-9892-4