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A New Approach for Gate-Level Delay-Insensitive Asynchronous Logic

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Abstract

We present a new approach for gate-level delay-insensitive asynchronous logic. The new approach uses only conventional synchronous synthesis and computer-aided design tools, as well as conventional standard cell libraries. This new design approach is highly suitable for very low voltage operation compared with traditional static CMOS design. An auto-sleep mode together with supply voltage control logic reduces leakage power consumption. Several benchmark circuits are implemented using IBM 130nm technology to show that the new asynchronous logic approach is robust even when operating in the sub-threshold regime. The layout for each benchmark is generated using Cadence’s automatic placement and routing tool. Hspice simulations for both asynchronous and synchronous versions of the benchmark circuits enabled comparison of the delay, area and leakage current. Monte Carlo simulations are performed for each benchmark circuit to demonstrate delay insensitivity for very low supply voltages with substantial threshold voltage (\(V_{T}\)) variations.

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  1. The University of Texas at Dallas, Richardson, TX, 75080, USA

    Zhao Wang, Xiao He & Carl Sechen

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  1. Zhao Wang
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  2. Xiao He
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  3. Carl Sechen
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Correspondence to Zhao Wang.

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Wang, Z., He, X. & Sechen, C. A New Approach for Gate-Level Delay-Insensitive Asynchronous Logic. Circuits Syst Signal Process 34, 1431–1459 (2015). https://doi.org/10.1007/s00034-014-9917-z

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