Abstract
A dynamic–static mixed range-matching scheme is proposed, which significantly increases system clock frequency and reduces \(\hbox {Energy-T}_{\mathrm {clock}}\)-Product (ETP). Furthermore, the range-matching cell adopted in the current scheme presents higher-speed performance although it uses two transistors less than the previous one. Using 1.2V SMIC 130 nm process, the proposed 16-bit range-matching word (RMW) can work in the minimal clock cycle of 0.753 ns. In case of 50 % duty cycle ratio and the minimal clock cycle, the ETP of proposed RMW is 5.947 fJ \(\cdot \) ns/bit/search.
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Acknowledgments
This work was financially supported by the National Natural Science Foundation of China ( Grant Nos. 61306091, 61131004, 61340050, 61474012) and the Fundamental Research Funds for the Central Universities ( Grant No.: DUT15QT46).
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Zhang, J., Yin, C., Wu, G. et al. High-Frequency and ETP-Efficient Range-Matching Scheme. Circuits Syst Signal Process 35, 3405–3417 (2016). https://doi.org/10.1007/s00034-015-0207-1
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DOI: https://doi.org/10.1007/s00034-015-0207-1