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LTE Turbo Decoding Parallel Architecture with Single Interleaver Implemented on FPGA

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Abstract

This paper describes the implementation on field programmable gate array (FPGA) of a turbo decoder for 3GPP Long-Term Evolution standard. Considering the high data rates required by this standard, parallel decoding architecture is used. The parallel decoding latency is reduced N times compared with the serial decoding latency, N being the parallelization factor, usually a power of 2. The decoding performances are similar for both serial and parallel schemes, when very low decoding latency is added to this theoretical parallel latency value. Taking advantage of the quadratic permutation polynomial interleaver properties, and considering some specific FPGA block memory characteristics, a novel simplified parallel decoding scheme is proposed, including only one interleaver, independently of the N value. Moreover, for the single interleaver, we propose a solution that exploits key arithmetic properties of the corresponding equation to perform the address computation in a recursive manner. The proposed method replaces divisions and multiplications by comparisons and subtractions. In addition, an even-odd merge sorting network provides correct data to all N decoding units.

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References

  1. 3GPP TS 36.212 V8.7.0 (2009-05) Technical specification, 3rd generation partnership project, technical specification group radio access network. Evolved Universal Terrestrial Radio Access (E-UTRA); Multiplexing and channel coding (Release 8)

  2. C. Anghel, A. A. Enescu, C. Paleologu, S. Ciochină, CTC turbo decoding architecture for H-ARQ capable WiMAX systems implemented on FPGA, in Proceedings of the International Conference on Networks (ICN) (2010), pp. 65–70

  3. C. Anghel, V. Stanciu, C. Stanciu, C. Paleologu, CTC turbo decoding architecture for LTE systems implemented on FPGA, in Proceedings of the International Conference on Networks (ICN) (2012), pp. 199–204

  4. R. Asghar, D. Wu, J. Eilert, D. Liu, Memory conflict analysis and a re-configurable interleaver architecture supporting unified parallel turbo decoding. J. Signal Process. Syst. 60, 15–19 (2010)

    Article  Google Scholar 

  5. K.E. Batcher, Sorting networks and their applications. Proceedings of the AFIPS Spring Joint Computing Conference 32, 307–314 (1968)

    Google Scholar 

  6. C. Berrou, A. Glavieux, Near optimum error correcting coding and decoding: Turbo-codes. IEEE Trans. Commun. 44, 1261–1271 (1996)

    Article  Google Scholar 

  7. C. Berrou, M. Jézéquel, Non binary convolutional codes for turbo coding. Electron. Lett. 35, 9–40 (1999)

    Article  Google Scholar 

  8. C. Berrou, A. Glavieux, P. Thitimajshima, Near Shannon limit error-correcting coding and decoding: Turbo codes, in Proceedings of the IEEE International Conference on Communications (ICC) (1993), pp. 1064–1070

  9. S. Chae, A low complexity parallel architecture of turbo decoder based on QPP interleaver for 3GPP-LTE/LTE-A. http://www.design-reuse.com/articles/31907/turbo-decoder-architecture-qpp-interleaver-3gpp-lte-lte-a.html (2012). Accessed 30 June 2016

  10. J.-F. Cheng, T. Ottosson, Linearly approximated log-MAP algorithms for turbo decoding, in Proceedings of the IEEE Vehicular Technology Conference (VTC) (2000), pp. 2252–2256

  11. C. Condo, VLSI decoding architectures: flexibility, robustness and performance, PhD thesis, Porto Institutional Repository, Politecnico di Torino, Italy, 2015

  12. C. Condo, A. Baghdadi, G. Masera, Reducing the dissipated energy in multi-standard turbo and LDPC decoders. Circuits, Syst. Signal Process. 34, 1571–1593 (2014)

    Article  MathSciNet  Google Scholar 

  13. A. Joshi, J. Zhang, D.S. Saini, Performance analysis and PAPR reduction of coded OFDM (with RS-CC and turbo coding) systems using modified SLM, PTS and DHT recoding in fading environments. WSEAS Trans. Commun. 12, 14–28 (2013)

    Google Scholar 

  14. F. Khan, LTE for 4G Mobile Broadband (Cambridge University Press, New York, 2009)

    Book  Google Scholar 

  15. Massachusetts Institute of Technology, Mathematics. http://math.mit.edu/~goemans/18310S15/batcher-notes (2015). Accessed 30 June 2016

  16. E. Mumolo, G. Capello, M. Nolich, VHDL design of a scalable VLSI sorting device based on pipelined computation. J. Comput. Inf. Technol. 12, 1–14 (2004)

    Article  Google Scholar 

  17. S. Papaharalabos, P. Sweeney, B.G. Evans, Constant log-MAP decoding algorithm for duo-binary turbo codes. Electron. Lett. 42, 709–710 (2006)

    Article  Google Scholar 

  18. D. Prasad, M. Y. M. Yusof, S. S. Palai, A. H. Nawi, Sorting networks on FPGA, in Proceedings of the WSEAS International Conference on Telecommunications and Informatics (TELE-INFO) (2011), pp. 29–31

  19. R. Robertson, E. Villebrun, P. Hoeher, A comparison of optimal and sub-optimal MAP decoding algorithms operating in the log domain, in Proceedings of the IEEE International Conference on Communications (ICC) (1995), pp. 1009–1013

  20. C. Studer, C. Benkeser, S. Belfanti, Q. Huang, Design and implementation of a parallel turbo-decoder ASIC for 3GPP-LTE. IEEE J. Solid-State Circuits 46, 8–17 (2011)

    Article  Google Scholar 

  21. Y. Sun, J.R. Cavallaro, Efficient hardware implementation of a highly-parallel 3GPP LTE/ LTE-advance turbo decoder. Integration 44, 305–315 (2011)

    Google Scholar 

  22. S. Syed Ameer Abbas, S.J. Thiruvengadam, FPGA implementation of 3 GPP-LTE physical downlink control channel using diversity techniques. WSEAS Trans. Signal Process. 9, 84–97 (2013)

    Google Scholar 

  23. Third Generation Partnership Project, 3GPP home page. www.3gpp.org. Accessed 30 June 2016

  24. M.C. Valenti, J. Sun, The UMTS turbo code and an efficient decoder implementation suitable for software-defined radios. Int. J. Wirel. Inf. Netw. 8, 203–215 (2001)

    Article  Google Scholar 

  25. S. Wang, L. Liu, Z. Wen, High speed QPP generator with optimized parallel architecture for 4G LTE-A system. Int. J. Adv. Comput. Technol. 4, 355–364 (2010)

    Google Scholar 

  26. D. Wu, R. Asghar, Y. Huang, D. Liu, Implementation of a high-speed parallel turbo decoder for 3GPP LTE terminals, in Proceedings of the IEEE International Conference on ASIC (ASICON) (2009), pp. 481–484

  27. Xilinx Virtex 5 family user guide. www.xilinx.com (2008). Accessed 30 June 2016

  28. Xilinx ML507 evaluation platform user guide. www.xilinx.com (2011). Accessed 30 June 2016

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Acknowledgments

The authors would like to thank the Editor-in-Chief and the reviewers for the valuable comments and suggestions.

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Authors and Affiliations

  1. University Politehnica of Bucharest, Bucharest, Romania

    Cristian Anghel, Cristian Stanciu & Constantin Paleologu

Authors
  1. Cristian Anghel
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  2. Cristian Stanciu
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  3. Constantin Paleologu
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Corresponding author

Correspondence to Cristian Anghel.

Additional information

This work has been funded by the Sectoral Operational Programme Human Resources Development 2007–2013 of the Ministry of European Funds through the Financial Agreement POSDRU/159/1.5/S/134398, and it was also supported by UEFISCDI Romania under Grant PN-II-RU-TE-2014-4-1880.

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Anghel, C., Stanciu, C. & Paleologu, C. LTE Turbo Decoding Parallel Architecture with Single Interleaver Implemented on FPGA. Circuits Syst Signal Process 36, 1455–1475 (2017). https://doi.org/10.1007/s00034-016-0362-z

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  • DOI: https://doi.org/10.1007/s00034-016-0362-z

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