Abstract
Leakage power dissipation is a serious concern in deep nanometer devices. Low power design methodology is often adopted in VLSI circuits and systems to minimize power; however, this is achieved at the cost of performance penalty. In this paper, we first review the existing circuit techniques for leakage minimization. A new circuit technique is then proposed which is designed intelligently by mixing a pair of dynamic threshold sleep transistors and a pair of helper transistors. The performance of the proposed technique is investigated in terms of area, power, delay and power–delay product. Extensive SPICE simulation with 32 nm process technology shows a significant reduction in power, delay and power–delay product.
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Abbreviations
- DTMOS:
-
Dynamic threshold MOS
- MTCMOS:
-
Multi-threshold CMOS
- LFA:
-
Leakage feedback approach
- SKA:
-
Sleepy keeper approach
- DG:
-
Drain gating
- PUN:
-
Pull-up network
- PDN:
-
Pull-down network
- PDP:
-
Power–delay product
- LCTs:
-
Leakage control transistors
- \({V}_{\mathrm{t}}\) :
-
Threshold voltage
- GLBB:
-
Gate-level body bias
- DLSL:
-
Dynamic logic suppression logic
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Lorenzo, R., Chaudhury, S. Dynamic Threshold Sleep Transistor Technique for High Speed and Low Leakage in CMOS Circuits. Circuits Syst Signal Process 36, 2654–2671 (2017). https://doi.org/10.1007/s00034-016-0442-0
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DOI: https://doi.org/10.1007/s00034-016-0442-0