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Design of Low-Power Voltage Scalable Arithmetic Units with Perfect Timing Error Cancelation

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Abstract

Many of the existing supply voltage overscaling (VOS) techniques allow an increase in the critical path delay, resulting in the reduction in the throughput rate. On the contrary, the VOS techniques without affecting on the throughput rate induce loss of the system performance by timing errors. In this paper, we propose a perfect timing error cancelation (PTEC) system which not only retains the throughput rate, but also perfectly recovers the system performance. In the arithmetic units whose output bits are sequentially computed, it is observed that timing violations due to VOS occur at some designated highest order output bits, resulting in the large error on the output value. By exploiting this property, a novel timing error cancelation technique is presented by modeling the timing error signal and deriving the condition for the perfect recovery from the impaired signal. The proposed PTEC system is verified with the design example of a 16\(\times \)16 unsigned carry-save multiplier. From simulation results, it is found that the proposed PTEC system with 200 mV overscaling offers 38% power reduction with maintaining the throughput rate as well as the system functionality compared to the conventional design with the nominal supply voltage (=1 V).

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Notes

  1. Note that the condition (5) is valid for generic arithmetic units, not specific to particular architecture.

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Acknowledgements

This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (NRF-2014R1A1A2055805), the ICT program of MSIP/IITP, Republic of Korea [B0101-16-1347], and the National Research Foundation (NRF) of Korea (Grant NRF-2015M1A3A3A02010753).

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Authors and Affiliations

  1. School of Electronics and Information, Kyung Hee University, Suwon, 446-701, Korea

    Ik Joon Chang

  2. Department of Electronic Engineering, Myongji University, Yongin, 449-728, Korea

    Sang Yoon Park

  3. Department of Electrical Engineering, Hanyang University, Seoul, 133-791, Korea

    Jun Won Choi

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  1. Ik Joon Chang
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  2. Sang Yoon Park
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  3. Jun Won Choi
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Correspondence to Jun Won Choi.

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Chang, I.J., Park, S.Y. & Choi, J.W. Design of Low-Power Voltage Scalable Arithmetic Units with Perfect Timing Error Cancelation. Circuits Syst Signal Process 36, 4309–4325 (2017). https://doi.org/10.1007/s00034-017-0534-5

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