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Improved Performance of Error Controlling Codes Using Pass Transistor Logic

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Abstract

System-on-ship (SoC) design in the nanoelectronics era brings us not only many opportunities but also several challenges like synchronization, process uncertainty, global interconnecting delay, high scalability, and reliability. Network on Chip (NoC) could be a communication subsystem and it is rising as a revolutionary design methodology to solve the problems associated with SoC designing. Reliability is one of the major designing challenges in NoC design under technology limitations at low voltage operations and under the influence of very deep sub-micron noise sources, including crosstalk noise. To achieve the reliability of NoC, error controlling codes (ECC) are required. ECCs are broadly categorized as forward error correcting (FEC) codes and error detection codes. ECC improves the reliability of NoC with a penalty of overhead power, delay, and area. In this paper, an attempt has been made to reduce the overhead power, delay and area of FEC codes: hamming code and dual rail code, and error detecting codes: checksum and two-dimensional parity with duplication. These ECC are designed in 65 nm technology using CMOS and pass transistor logic and their power–reliability trade-off is analyzed and compared in terms of delay and overhead area. From the results, it is observed that error controlling schemes are providing the best performance with pass transistor logic over error controlling schemes with CMOS logic.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, RGMCET, Nandyal, Andhra Pradesh, 518501, India

    M. Chennakesavulu & T. Jayachandra Prasad

  2. Department of Electronics and Communication Engineering, JNTUA, Ananthapuramu, Andhra Pradesh, 515001, India

    V. Sumalatha

Authors
  1. M. Chennakesavulu
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  2. T. Jayachandra Prasad
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  3. V. Sumalatha
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Correspondence to M. Chennakesavulu.

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Chennakesavulu, M., Jayachandra Prasad, T. & Sumalatha, V. Improved Performance of Error Controlling Codes Using Pass Transistor Logic. Circuits Syst Signal Process 37, 1145–1161 (2018). https://doi.org/10.1007/s00034-017-0596-4

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  • DOI: https://doi.org/10.1007/s00034-017-0596-4

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