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Versatile Quaternion Multipliers Based on Distributed Arithmetic

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Abstract

This paper introduces the idea of versatile circuits for multiplying 4-dimensional hypercomplex numbers in hardware. Depending on the settings of such a device, a variable quaternion can be left- or right-multiplied by a constant coefficient or by its conjugate, as various operations are useful in transform-type algorithms. Multiplierless circuits based on distributed arithmetic (DA) are reviewed that compute quaternion products by additions and bit shifts. It is shown that they can be made versatile by extending memory of partial results, but a better solution is our method for preprocessing bits used to address this memory. The method allows for using the same partial results to compute different inner products that are related to a quaternion multiplication. So versatile multipliers can be implemented with memory optimized so as to save area or to speed up reprogramming compared to the basic DA-based circuit. This has been demonstrated by hardware design experiments, which show that 13–69% area can be saved in a case of ASIC implementation, while for FPGA implementation, spending only 11% more logic resources allows a multiplier to be reprogrammed 75% faster. Additionally, it has been explained how versatile multipliers can be used to realize low-area analysis/synthesis filter banks.

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Notes

  1. As to \(\tilde{\varvec{\Lambda }}(z)\) and \(\varvec{\Lambda }(z)\), they are inverses of each other up to delay, \(\tilde{\varvec{\Lambda }}(z) = \varvec{\Lambda }^{-1}(z) z^{-1} \). This makes the synthesis filters causal at the price of reconstructing a delayed copy of the input signal.

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Authors and Affiliations

  1. Department of Digital Media and Computer Graphics, Bialystok University of Technology, Wiejska 45A, 15-351, Bialystok, Poland

    Marek Parfieniuk

  2. Department of Electronic Engineering, Myongji University, Yongin, 17058, Korea

    Sang Yoon Park

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  1. Marek Parfieniuk
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  2. Sang Yoon Park
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Correspondence to Sang Yoon Park.

Additional information

This work was supported by Bialystok University of Technology under Grand S/WI/3/2018 and 2016 Research Fund of Myongji University.

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Parfieniuk, M., Park, S.Y. Versatile Quaternion Multipliers Based on Distributed Arithmetic. Circuits Syst Signal Process 37, 4880–4906 (2018). https://doi.org/10.1007/s00034-018-0789-5

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  • DOI: https://doi.org/10.1007/s00034-018-0789-5

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