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Hardware Optimized FPGA Implementations of High-Speed True Random Bit Generators Based on Switching-Type Chaotic Oscillators

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Abstract

One of the important applications of chaotic oscillators is their employment as sources of entropy for True Random Bit Generators (TRBGs). In this work, we introduce high-speed TRBGs realized on a modular Field Programmable Gate Array (FPGA) hardware platform using two different switching-type chaotic oscillators. While both oscillators are autonomous, one is 3-D and the other is 4-D. This enables us to investigate and compare the advantages/disadvantages of higher dimensional chaotic oscillators on the throughput, hardware requirements and security of the generated bit-streams. For that purpose, two different implementations are described for each TRBG; a throughput-optimized architecture and a resource-optimized architecture that utilizes fewer FPGA blocks. In both cases, high speed is achieved by concatenating all state-space variables of each chaos generator into one variable. Furthermore, a new postprocessing method that enables the generated bit-streams to pass all NIST 800.22 statistical tests is introduced. Experimental results show that the throughput-optimized TRBG architecture, based on the 4-D system, can exceed 1882 Mbit/s. However, the resource-optimized TRBG architecture, based on the 3-D system, is the best in terms of FPGA resources and overall Figure of Merit.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, College of Engineering, University of Sharjah, PO Box 27272, Sharjah, United Arab Emirates

    Talal Bonny, Ridhwan Al Debsi, Sohaib Majzoub & Ahmed S. Elwakil

  2. Nano-electronics Integrated Systems Center, Nile University, Cairo, Egypt

    Ahmed S. Elwakil

  3. Department of Electrical and Computer Engineering, University of Calgary, Calgary, Alberta, Canada

    Ahmed S. Elwakil

Authors
  1. Talal Bonny
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  2. Ridhwan Al Debsi
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  3. Sohaib Majzoub
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  4. Ahmed S. Elwakil
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Correspondence to Ahmed S. Elwakil.

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Bonny, T., Al Debsi, R., Majzoub, S. et al. Hardware Optimized FPGA Implementations of High-Speed True Random Bit Generators Based on Switching-Type Chaotic Oscillators. Circuits Syst Signal Process 38, 1342–1359 (2019). https://doi.org/10.1007/s00034-018-0905-6

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  • DOI: https://doi.org/10.1007/s00034-018-0905-6

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