Abstract
This paper presents a power/delay/area performance-improved radix-4 8 × 8 Booth multiplier. The major modification for reducing delay is a parallel structure for the addition of encoded partial products. Additional enhancements include an optimized Booth encoder, an optimized B2C design, and a unique square root carry-select adder with carry-lookahead adder logic to minimize multiplier’s delay. This design achieved a reduction of 26.6% in power consumption, 15% in area consumption, and 25.6% in data arrival time compared to recently published similar designs. All the proposed circuits were designed and synthesized in Synopsys CMOS 32 nm technology.
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Boppana, N.V.V.K., Kommareddy, J. & Ren, S. Low-Cost and High-Performance 8 × 8 Booth Multiplier. Circuits Syst Signal Process 38, 4357–4368 (2019). https://doi.org/10.1007/s00034-019-01044-x
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DOI: https://doi.org/10.1007/s00034-019-01044-x