Abstract
In VLSI physical design, floorplanning is an important step. When there is a substantial increase in the number of modules in circuits, physical design automation tools stand in need of efficient algorithms. This paper proposes a new algorithm, namely B*tree crossover simulated annealing algorithm (BCSA), for fixed-outline floorplanning problem. This work aims to minimize dead space with the objective of optimizing area and wire length. A novel crossover in B*tree is introduced with the efficient simulated annealing algorithm. Proposed approaches improve the exploration capabilities of simple simulated annealing algorithm. BCSA is tested on famous Microelectronics Center of North Carolina benchmark circuits. Results are comparatively better than most of the state-of-the-art algorithms. BCSA produces less dead space. BCSA algorithm is found more efficient for problems of larger sizes.
Similar content being viewed by others
References
S.N. Adya, I.L. Markov, Fixed-outline floorplanning through better local search, in ICCD’01: Proceedings of the International Conference on Computer Design. VLSI in Computers & Processors (IEEE Computer Society, Austin, 2001), pp. 328–334
S.N. Adya, I.L. Markov, Fixed-outline floorplanning: enabling hierarchical design. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 11(6), 1120–1135 (2003)
S. Anand, S. Saravanasankar, P. Subbaraj, Customized simulated annealing based decision algorithms for combinatorial optimization in VLSI floorplanning problem. Comput. Optim. Appl. 52(3), 667–678 (2012)
C.J. Alpert, D.P. Mehta, S.S. Sapatnekar, Handbook of Algorithms for Physical Design Automation, 1st edn. (CRC Publishers, Boston, 2008)
Y C. Chang, Y.W. Chang, G.M. Wu, S.W. Wu, B*-trees: a new representation for non-slicing floorplans, in Proceedings of the 37th Design Automation Conference (2000), pp. 458–463. https://doi.org/10.1109/DAC.2000.855354
J. Chen, G. Chen, W. Guo, A discrete PSO for multi-objective optimization in VLSI floorplanning, in Internatioal Symposium on Intelligence Computation and Applications (2009), pp. 400–410
G. Chen, W. Guo, Y.A. Chen, A PSO-based intelligent decision algorithm for VLSI floorplanning. Soft Comput. Fusion Found. Methodol. Appl. 14(12), 1329–1337 (2010). https://doi.org/10.1007/s00500-009-0501-6
T.C. Chen, Y.W. Chang, Modern floorplanning based on fast simulated annealing. IEEE Trans. CAD 25(4), 510–522 (2006)
C.K. Cheng, T. Yoshimura, An enhanced perturbing algorithm for floorplan design using the O-tree representation, in Proceedings of International Symposium on Physical Design (2000), pp. 168–173
L. Christine Valenzuela, Y. Pearl Wang, A genetic algorithm for VLSI floorplanning, in Proceedings of the 6th International Conference on Parallel Problem Solving from Nature (2000), pp. 671–680
L. Christine Valenzuela, Y. Pearl Wang, VLSI placement and area optimization using a genetic algorithm to breed normalized postfix expressions. IEEE Trans. Evol. Comput. 6(4), 390–401 (2002)
P.N. Guo, C.K. Cheng, T. Yoshimura, An O-tree representation of non-slicing floorplans and its applications, in Proceedings of ACM/IEEE Design Automation Conference (ACM, New York, 1999), pp. 268–273
C.S. Hoo, K. Jeevan, V. Ganapathy, H. Ramiah, Variable-order ant system for VLSI multi objective floorplanning. Appl. Soft Comput. 13(7), 3285–3297 (2013)
S. Kirpatrick, C.D. Gelatt, M.P. Vecchi, Optimization by simulated annealing. Science 220(4598), 671–680 (1983)
J.M. Lin, Y.W. Chang, TCG: a transitive closure graph-based representation for non-slicing floorplans, in Proceedings of the 38th Conference on Design Automation Las Vegas, Nevada (2001), pp. 764–769
J.M. Lin, Y.W. Chang, S.P. Lin, Corner Sequence: a P-admissible floorplan representation with a worst-case linear-time packing scheme. IEEE Trans. VLSI Syst. 11(4), 679–686 (2003)
T. Lin, D.S. Chen, Y.W. Wang, Robust fixed-outline floorplanning through evolutionary search, in ASP-DAC’04: Proceedings of the 2004 Asia and South Pacific Design Automation Conference (IEEE Press, Piscataway, 2004), pp. 42–44
H. Murtha, E.S. Kuh, Sequence pair-based placement method for hard/soft/pre-placed modules, in ISPD’98: Proceedings of the 1998 International Symposium on Physical Design (ACM, New York, 1998), pp. 167–172. https://doi.org/10.1145/274535.274560
M. Tang, X. Yao, A memetic algorithm for VLSI floorplanning. IEEE Trans. Syst. Man Cybern. 37(1), 123–135 (2007)
M. Tang, A. Sebastian, A genetic algorithm for VLSI floorplanning using O-tree representation, in Applications on Evolutionary Computing. Lecture Notes in Computer Science, vol. 3449 (Springer, Berlin, 2005), pp. 215–224
D.F. Wong, H.W. Leong, C.L. Liu, Simulated Annealing for VLSI Design (Kluwer Academic Publishers, Norwell, 1988)
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher’s Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Shunmugathammal, M., Christopher Columbus, C. & Anand, S. A Novel B*tree Crossover-Based Simulated Annealing Algorithm for Combinatorial Optimization in VLSI Fixed-Outline Floorplans. Circuits Syst Signal Process 39, 900–918 (2020). https://doi.org/10.1007/s00034-019-01054-9
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00034-019-01054-9