Abstract
Conventional two-dimensional filters for digital image processing are computationally intensive and consume significant hardware resources on field-programmable gate array (FPGA). Multiple filters implemented at a very low area and power budget are essential requirements of modern embedded systems for performing diversified image processing tasks. The previously reported multi-filter architectures are infeasible, since they do not provide pareto-optimal solution in terms of flexibility, hardware cost and versatility. This work presents a pareto-optimal multi-filter architecture that cater to these three major design concerns. The high degree of flexibility is induced in design by the deployment of an efficient customized 2,3 tree structure. This implements successive odd filter kernels in 44 different combinations with the maximum \(9 \times 9\) size, without hardware blocking. These implemented filters are structurally optimized and versatile for realizing diverse filter types at a very low cost. The complete design occupies only 2319 Slices on Xilinx Artix-7 FPGA and performs at 111 fps for full HD resolution with a very low power consumption of 197.5 mW. With these attributes, the proposed multi-filter architecture implements multiple filters of diverse types at very low area and power; this makes it well suited for image processing applications in real time. Finally, the proposed architecture is validated using Digilent Nexys4 development board.
Similar content being viewed by others
References
Altera, Guidance for Accurately Benchmarking FPGAs(ver. 1.2) (2007)
APU, Application Processor Unit, XA Zynq-7000 All Programmable SoC First Generation Architecture (2012)
APU, Application Processor Unit, Zynq-7000 All Programmable SoC Overview (2012)
D.G. Bailey, Design for Embedded Image Processing on FPGAs (Wiley, London, 2011)
F. Bashar, A. Khan, F. Ahmed, H. Kabir, Face recognition using similarity pattern of image directional edge response. Adv. Electr. Comput. Eng. 14(1), 69–76 (2014)
B. Bosi, G. Bois, Y. Savaria, Reconfigurable pipelined 2-D convolvers for fast digital signal processing. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7(3), 299–308 (1999)
A. Epstein, Parallel Hardware Architectures for the Life Sciences (Delft University of Technology, Delft, TU Delft, 2004)
L. Fiack, N. Cuperlier, B. Miramond, Embedded and real-time architecture for bio-inspired vision-based robot navigation. J. Real Time Image Process. 10(4), 699–722 (2015)
D. Frejlichowski, R. Wanat, Application of the laplacian pyramid decomposition to the enhancement of digital dental radiographic images for the automatic person identification, in International Conference Image Analysis and Recognition (Springer, Berlin, 2010), pp. 151–160
A.A. Gonzalez, M.A. Estrada, M.P. Patricio, J.L.C. Anzueto, An FPGA 2D-convolution unit based on the CAPH language. J. Real Time Image Process. (2015). https://doi.org/10.1007/s11554-015-0535-1
R.C. Gonzalez, R.E. Woods, Digital Image Processing, 2nd edn. (Prentice Hall, USA, 2002)
P. Gu, W.M. Lee, M.A. Roubidoux, J. Yuan, X. Wang, P.L. Carson, Automated 3D ultrasound image segmentation to aid breast cancer image interpretation. Ultrasonics 65, 51–58 (2016)
M. Kazmi, A. Aziz, P. Akhtar, N. Ikram, A low cost structurally optimized design for diverse filter types. PLoS ONE 11(11), e0166056 (2016)
M. Kazmi, A. Aziz, P. Akhtar, N. Ikram, A FPGA based Reconfigurable 2D filter architecture for biomedical image preprocessing. Casp. J. Appl. Sci. Res. 5(2), 1–10 (2016)
M. Kazmi, A. Aziz, P. Akhtar, An efficient and compact row buffer architecture on FPGA for real-time neighbourhood image processing. J. Real Time Image Process. (2017). https://doi.org/10.1007/s11554-017-0690-7
S. Kockanat, N. Karaboga, The design approaches of two-dimensional digital filters based on metaheuristic optimization algorithms: a review of the literature. Artif. Intell. Rev. 44, 265–287 (2015)
Nexys 4 FPGA Board Reference Manual Technical Report, Digilent (2016)
G. Paun, G. Rozenberg, A. Salomaa, Current Trends in Theoretical Computer Science: Algorithms and complexity, vol. 1 (World Scientific, Singapore, 2004)
K. Pauwels, M. Tomasi, J.D. Alonso, E. Ros, M.M. Van Hulle, A comparison of FPGA and GPU for real-time phase-based optical flow, stereo, and local image features. IEEE Trans. Comput. 61(7), 999–1012 (2012)
A. Percey, Advantages of the Virtex-5 FPGA 6-Input LUT Architecture (WP284 (v1.0)) (2007)
S. Perri, P. Corsonello, VLSI implementations of efficient isotropic flexible 2D convolvers. IET Circuits Devices Syst. 1(4), 263–269 (2007)
S. Perri, M. Lanuzza, P. Corsonello, G. Cocorullo, A high-performance fully reconfigurable FPGA-based 2D convolution processor. Microprocess. Microsyst. 29(8), 381–391 (2005)
L. Rao, B. Zhang, J. Zhao, Hardware implementation of reconfigurable 1D convolution. J. Signal Process. Syst. 82, 1–16 (2015)
H.C. Reddy, I.H. Khoo, P.K. Rajan, Application of symmetry: 2-D polynomials, fourier transform, and filter design, in The Circuits and Filters Handbook, ed. by W.K. Chen, 3rd edn. (CRC, Boca Raton, FL, 2009), p. 20
M. Rogawski, K. Gaj, A high-speed unified hardware architecture for AES and the SHA-3 candidate Grostl, in 15th Euromicro Conference on Digital System Design (DSD) (IEEE, 2012), pp. 568–575
J. Vourvoulakis, J. Kalomiros, J. Lygouras, Fully pipelined FPGA-based architecture for real-time SIFT extraction. Microprocess. Microsyst. 40, 53–73 (2016)
T. White, D. OLeary, V. Magnotta, S. Arndt, M. Flaum, N.C. Andreasen, Anatomic and functional variability: the effects of filter size in group fMRI data analysis. Neuroimage 13(4), 577–588 (2001)
Xilinx Inc., 7 Series FPGAs Configurable Logic Block (UG474 (v1.6)) (2014)
Xilinx, Virtex-E 1.8 V Field Programmable Gate Arrays (DS022-1 (v3.0)) (2014)
J. Yasmin, M. Sathik, An improved iterative segmentation algorithm using canny edge detector for skin lesion border detection. Int. Arab J. Inf. Technol. (IAJIT) 12(4), 325–332 (2015)
B. Zhang, K. Mei, N. Zheng, Coarse-grained dynamically reconfigurable processor for vision pre-processing. J. Signal Process. Syst. 79, 1–17 (2013)
M.Z. Zhang, V.K. Asari, A design methodology for performance-resource optimization of a generalized 2D convolution architecture with quadrant symmetric kernels, in Advances in Computer Systems Architecture. ACSAC 2007. Lecture Notes in Computer Science, vol. 4697. (Springer, Berlin), pp. 220–234
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Kazmi, M., Aziz, A. & Kundi, DeS. A Pareto-Optimal Multi-filter Architecture on FPGA for Image Processing Applications. Circuits Syst Signal Process 38, 4762–4786 (2019). https://doi.org/10.1007/s00034-019-01083-4
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00034-019-01083-4