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Second Minimum Approximation for Min-Sum Decoders Suitable for High-Rate LDPC Codes

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Abstract

In this paper, a method to approximate the second minimum required in the computation of the check node update of an LDPC decoder based on min-sum algorithm is presented. The proposed approximation compensates the performance degradation caused by the utilization of a first minimum and pseudo-second minimum finder instead of a true two minimum finder in the min-sum algorithm and improves the BER performance of high-rate LDPC codes in the error floor region. This approach applied to a complete decoder reduces the critical path and the area with independence of the selected architecture. Therefore, this method increases the maximum throughput achieved by the decoder and its area-throughput efficiency. The increase in efficiency is proportional to the degree of the check node, so the higher the code rate is, the higher the improvement in area and speed is.

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Notes

  1. It is assumed, without loss of generality, that the \(d_\mathrm{c}\) messages are identically distributed.

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Authors and Affiliations

  1. iTEAM, Universitat Politècnica de València, 46730, Gandia, Spain

    J. M. Català-Pérez

  2. ARIES Research Center, Universidad Antonio de Nebrija, C/ Pirineos, 55, 28040, Madrid, Spain

    F. García-Herrero

  3. IMDEA Networks Institute, 28918, Madrid, Spain

    J. O. Lacruz

  4. ETIS Laboratory, ENSEA, CNRS-UMR-8051, Univ. Cergy-Pontoise, 6, Avenue du Ponceau, 95000, Cergy-Pontoise, France

    David Declercq

  5. Instituto de Telecomunicaciones y Aplicaciones Multimedia (ITEAM), Universitat Politècnica de València, 46022, València, Spain

    J. Valls

Authors
  1. J. M. Català-Pérez
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  2. J. O. Lacruz
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  3. F. García-Herrero
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  4. J. Valls
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  5. David Declercq
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Correspondence to J. Valls.

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This research was supported by the Spanish Ministerio de Ciencia e Innovación and FEDER, under Grant No. TEC2015-70858-C2-2-R and partially funded by the Institut Universitaire de France.

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Català-Pérez, J.M., Lacruz, J.O., García-Herrero, F. et al. Second Minimum Approximation for Min-Sum Decoders Suitable for High-Rate LDPC Codes. Circuits Syst Signal Process 38, 5068–5080 (2019). https://doi.org/10.1007/s00034-019-01107-z

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  • DOI: https://doi.org/10.1007/s00034-019-01107-z

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