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High-Performance System-on-Chip-Based Accelerator System for Polynomial Matrix Multiplications

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Abstract

Polynomial matrix computations, such as polynomial matrix multiplication (PMM) and eigenvalue factorization of parahermitian matrices, have played an important role in a growing number of applications, in recent times. However, the computational complexity and expense of such operations impose a profound limit on their applicability. In a recent paper, we introduced a systolic array-based parallel architecture for PMM, which was adequately efficient, but limited in its application. In this paper, we propose a second-generation hardware solution which boasts more versatility, efficiency and scalability compared to our previous design. This is achieved through the design of a highly versatile PMM accelerator which supports polynomial matrices of any size, as a component of the embedded system developed within the Xilinx Zynq-7000 AP SoC. Experimental results demonstrate the efficiency and effectiveness of our novel SoC-based PMM accelerator in the context of subband coding, where maximum speedups of \(85\times \) and \(33\times \) are accomplished, without compromising the accuracy, in comparison with two highly optimized and multi-threaded software-only implementations running on a dual-core ARM Cortex-A9 processor and a Intel Core i7-4510U CPU, respectively.

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Authors and Affiliations

  1. School of Computer Science and Electronic Engineering, University of Essex, Essex, UK

    Server Kasap

  2. Faculty of Engineering, European University of Lefke, Lefke, Northern Cyprus, TR-10 Mersin, Turkey

    Soydan Redif

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  1. Server Kasap
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  2. Soydan Redif
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Correspondence to Server Kasap.

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Kasap, S., Redif, S. High-Performance System-on-Chip-Based Accelerator System for Polynomial Matrix Multiplications. Circuits Syst Signal Process 38, 5755–5785 (2019). https://doi.org/10.1007/s00034-019-01150-w

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