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A Low-Power and High-Frequency Phase Frequency Detector for a 3.33-GHz Delay Locked Loop

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Abstract

In this paper, a new design of a low-power and high-frequency phase frequency detector (PFD) is presented. Due to delay in the reset path, blind zone and dead zone, the maximum operating frequency in conventional PFDs is limited. The proposed structure uses two D flip-flops in true single-phase clock (TSPC) logic and an AND gate in gate-diffusion input (GDI) logic. Using just 16 transistors in this new structure achieves lower power consumption, and a short delay in the reset path enables the PFD to work at higher frequencies. The proposed circuit is simulated in Taiwan Semiconductor (TSMC) 0.18-µm complementary metal-oxide semiconductor (CMOS) technology. The simulated reset delay time is 150 ps in which the presented PFD operates at 3.33 GHz. The power consumption is 110 µW at a frequency of 3.33 GHz. Also, a delay locked loop (DLL) using the proposed PFD is simulated to approve the correct performance of the designed circuit at maximum frequency of 3.33 GHz. The power consumption of the presented DLL is 1.68 mW at this frequency.

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Authors and Affiliations

  1. Faculty of Electrical and Computer Engineering, Babol Noshirvani University of Technology, Babol, Iran

    Adel Rezaeian & Gholamreza Ardeshir

  2. Faculty of Engineering and Technology, University of Mazandaran, Babolsar, Iran

    Mohammad Gholami

Authors
  1. Adel Rezaeian
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  2. Gholamreza Ardeshir
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  3. Mohammad Gholami
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Correspondence to Mohammad Gholami.

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Rezaeian, A., Ardeshir, G. & Gholami, M. A Low-Power and High-Frequency Phase Frequency Detector for a 3.33-GHz Delay Locked Loop. Circuits Syst Signal Process 39, 1735–1750 (2020). https://doi.org/10.1007/s00034-019-01232-9

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  • DOI: https://doi.org/10.1007/s00034-019-01232-9

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