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Median Selection for Calibrating the Capacitor Mismatch to Improve the Linearity of Analog-to-Digital Converter

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Abstract

This paper presents a capacitor calibration technique called median selection for improving the static and dynamic performance of the successive approximation register (SAR) analog-to-digital converter (ADC). Monte Carlo simulations in MATLAB are presented to demonstrate the effect of the proposed method. Simulation results show that for an 18-bit RC-hybrid SAR ADC with the mismatch of the unit capacitor (\({\sigma _u} = {{{\sigma _0}}\big / {{C_u}}}\)) of 0.05%, the root mean square (rms) of differential nonlinearity is improved by 94.7%–0.23 LSB and the rms of integral nonlinearity is promoted by 96.7%–0.20 LSB by the proposed median selection. On the other hand, the median selection improves the mean value of the spurious free dynamic range from 94.09 to 128.85 dB, while the mean value of the signal-to-noise-and-distortion ratio is improved from 88.70 to 109.82 dB.

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Authors and Affiliations

  1. School of Electronic Science and Engineering, University of Electronic Science and Technology of China, Chengdu, China

    Hua Fan & Chen Wang

  2. School of Information Science and Technology, Southwest Jiaotong University, Chengdu, China

    Quanyuan Feng

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  1. Hua Fan
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  2. Chen Wang
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Correspondence to Hua Fan.

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The work of Hua Fan was supported by the National Natural Science Foundation of China (NSFC) under Grant 61771111, supported by Sichuan Provincial Science and Technology Important Projects under Grant 19ZDYF2863, as well as supported by China Postdoctoral Science Foundation under Grants 2017M612940 and 2019T120834 and Special Foundation of Sichuan Provincial Postdoctoral Science Foundation. The work of Quanyuan Feng was supported by the National Natural Science Foundation of China (NSFC) under Grant 61531016, supported by Sichuan Provincial Science and Technology Important Projects under Grants 2018GZ0139, 2018ZDZX0148, and 2018GZDZX0001.

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Fan, H., Wang, C. & Feng, Q. Median Selection for Calibrating the Capacitor Mismatch to Improve the Linearity of Analog-to-Digital Converter. Circuits Syst Signal Process 39, 5331–5351 (2020). https://doi.org/10.1007/s00034-020-01434-6

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  • DOI: https://doi.org/10.1007/s00034-020-01434-6

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