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A 0.3-V 8.72-nW OTA with Bulk-Driven Low-Impedance Compensation for Ultra-Low Power Applications

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Abstract

A bulk-driven low-impedance compensation technique is proposed for ultra-low supply voltage amplifiers. By using the low resistance node of the current mirror of input, the efficiency of Miller compensation capacitor is greatly improved. By using this compensation method, a rail-to-rail input & output bulk-driven fully differential operational amplifier is also presented in the paper. The effectiveness of the circuit has been verified in a 65 nm CMOS process, the proposed three-stage amplifier has over 70.69 dB gain, 19.95 kHz gain-bandwidth product, and 69.7° phase margin while consuming only 8.72 nW power, and occupying die area of 0.00082 mm2 from a 0.3 V supply while driving a 100pF load.

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References

  1. W. Bai, Z. Zhu, A 0.5-V 9.3-ENOB 68-nW 10-kS/s SAR ADC in 0.18-μm CMOS for biomedical applications. Microelectron. J. 59, 40–46 (2017). https://doi.org/10.1016/j.mejo.2016.11.007

    Article  Google Scholar 

  2. X. Tong, M. Song, Y. Chen, S. Dong, A 10-Bit 120 kS/s SAR ADC without reset energy for biomedical electronics. Circuits, Systems, and Signal Processing 38(12), 5411–5425 (2019). https://doi.org/10.1007/s00034-019-01138-6

    Article  Google Scholar 

  3. X. Tong, M. Ghovanloo, Multichannel wireless neural recording AFE architectures: Analysis, modeling, and tradeoffs. IEEE Design & Test 33(4), 24–36 (2016). https://doi.org/10.1109/MDAT.2015.2504367

    Article  Google Scholar 

  4. D. Li, M. Liu, L. Zhao, H. Mao, R. Ding, Z. Zhu, An 8-bit 2.1-mW 350-MS/s SAR ADC with 1.5 b/cycle redundancy in 65-nm CMOS express briefs. IEEE Trans. Circuits Syst. II (2020). https://doi.org/10.1109/TCSII.2020.2968457

    Article  Google Scholar 

  5. C. Cao, Q. Ye, Z. Zhu, Y. Yang, A background digital calibration of split-capacitor 16-bit SAR ADC with sub-binary architecture. Microelectron. J. 46(9), 795–800 (2015). https://doi.org/10.1016/j.mejo.2015.06.013

    Article  Google Scholar 

  6. W. Jiang, Y. Zhu, M. Zhang, C. Chan, R.P. Martins, A temperature-stabilized single-channel 1-GS/s 60-dB SNDR SAR-assisted pipelined ADC with dynamic Gm-r-based amplifier. IEEE J. Solid-State Circuits 55(2), 322–332 (2020). https://doi.org/10.1109/JSSC.2019.2948170

    Article  Google Scholar 

  7. J. Riad, J.J. Estrada-López, I. Padilla-Cantoya, E. Sánchez-Sinencio, Power-scaling output-compensated three-stage OTAs for wide load range applications. IEEE Trans. Circuits Syst. I Regul. Pap. 67(7), 2180–2192 (2020). https://doi.org/10.1109/TCSI.2020.2978515

    Article  Google Scholar 

  8. T. Kulej, F. Khateb, Design and implementation of sub 0.5-V OTAs in 0.18-μm CMOS. Int. J. Circuit Theory Appl. 46(6), 1129–1143 (2018). https://doi.org/10.1002/cta.2465

    Article  Google Scholar 

  9. Saxena, V., Baker, R.J. Indirect compensation techniques for three-stage CMOS op-amps. In: IEEE International Midwest Symposium on Circuits and Systems, (2009), pp.9–12

  10. Li, Z., Zhu, Z., Xie, Y., Liu, M. A 116 dB Gain, 556.1 MHz GBW Four-Stage OTA in 65 nm CMOS. In: IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), (2018), pp.1–3

  11. S. Dong, Z. Zhu, A transconductance-enhancement cascode Miller compensation for low-power multistage amplifiers. Microelectron. J. 73, 94–100 (2018). https://doi.org/10.1016/j.mejo.2018.01.009

    Article  Google Scholar 

  12. E. Ranjbar, M. Danaie, Frequency compensation of three-stage operational amplifiers: Sensitivity and robustness analysis. Microelectron. J. 66, 155–166 (2017). https://doi.org/10.1016/j.mejo.2017.06.010

    Article  Google Scholar 

  13. Yavari, M., Shoaei, O., Svelto, F. Hybrid cascode compensation for two-stage CMOS operational amplifiers. In: IEEE International Symposium on Circuits and Systems, (2005), pp. 1565–1568

  14. E. Zia, A. Jalali, M. Akbari, Indirect frequency compensation technique using flipped voltage follower cell. Int. J. Electron. Lett. 5(2), 189–198 (2017). https://doi.org/10.1080/21681724.2016.1138510

    Article  Google Scholar 

  15. S. Liu, Z. Zhu, J. Wang, L. Liu, Y. Yang, A 1.2-V 2.41-GHz three-stage CMOS OTA with efficient frequency compensation technique. IEEE Trans. Circuits Syst. I: Reg. Pap. 66(1), 20–30 (2019)

    Article  Google Scholar 

  16. J.H. Huijsing, D. Linebarger, Low-voltage operational amplifier with rail-to-rail input and output ranges. IEEE J. Solid-State Circuits 20(6), 1144–1150 (1985). https://doi.org/10.1109/JSSC.1985.1052452

    Article  Google Scholar 

  17. R.G.H. Eschauzier, L.P.T. Kerklaan, J.H. Huijsing, A 100-MHz 100-dB operational amplifier with multipath nested Miller compensation structure. IEEE J. Solid-State Circuits 27(12), 1709–1717 (1992). https://doi.org/10.1109/4.173096

    Article  Google Scholar 

  18. Xiaohong, P., Sansen, W. Nested feed-forward Gm-stage and nulling resistor plus nested-Miller compensation for multistage amplifiers. In: IEEE Custom Integrated Circuits Conference (CICC), (2002), pp.329–332

  19. F. Xiaohua, C. Mishra, E. Sanchez-Sinencio, Single Miller capacitor frequency compensation technique for low-power multistage amplifiers. IEEE J. Solid-State Circuits 40(3), 584–592 (2005). https://doi.org/10.1109/JSSC.2005.843602

    Article  Google Scholar 

  20. S. Biabanifard, S. Mehdi Largani, M. Akbari, S. Asadi, M.C.E. Yagoub, High performance reversed nested Miller frequency compensation. Analog Integr. Circuits Sig. Process. 85(1), 223–233 (2015). https://doi.org/10.1007/s10470-015-0616-x

    Article  Google Scholar 

  21. Liu, L., Zhuang, Y., Zhang, L., Jing, K., Dong, S., Chen, Y. A Reconfigurable Low Noise Amplifier with Sub-amplifier Compensation for Wearable Wireless Neural Recording System. In : IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), (2019), pp.1–3

  22. M. Akbari, O. Hashemipour, A 63-dB gain OTA operating in subthreshold with 20-nW power consumption. Int. J. Circuit Theory Appl. 45(6), 843–850 (2017). https://doi.org/10.1002/cta.2248

    Article  Google Scholar 

  23. Y. Wang, X. Zhao, Q. Zhang, X. Lv, Adjustably transconductance enhanced bulk-driven OTA with the CMOS technologies scaling. Electron. Lett. 54(5), 276–278 (2018). https://doi.org/10.1049/el.2017.4435

    Article  Google Scholar 

  24. H. Veldandi, R.A. Shaik, 2018 A 0.3-V pseudo-differential bulk-Input OTA for low-frequency applications. Circuits Syst. Sig. Process. 37(12), 5199–5221 (2018). https://doi.org/10.1007/s00034-018-0817-5

    Article  Google Scholar 

  25. Z. Qin, A. Tanaka, N. Takaya, H. Yoshizawa, 0.5-V 70-nW rail-to-rail operational amplifier using a cross-coupled output stage. IEEE Trans. Circuits Syst II: Exp Briefs 63(11), 1009–1013 (2016). https://doi.org/10.1109/TCSII.2016.2539081

    Article  Google Scholar 

  26. K. Woo, B. Yang, A 0.25-V rail-to-rail three-stage OTA with an enhanced DC gain. IEEE Trans. Circuits Syst. II: Exp. Briefs 67(7), 1179–1183 (2020). https://doi.org/10.1109/TCSII.2019.2935172

    Article  Google Scholar 

  27. T. Kulej, 0.5-V bulk-driven CMOS operational amplifier. IET Circuits Dev. Syst. 7, 352–360 (2013). https://doi.org/10.1049/iet-cds.2012.0372

    Article  Google Scholar 

  28. T. Kulej, F. Khateb, A 0.3-V 98-dB rail-to-rail OTA in $0.18~\mu$ m CMOS. IEEE Access 8, 27459–27467 (2020). https://doi.org/10.1109/ACCESS.2020.2972067

    Article  Google Scholar 

  29. T. Kulej, F. Khateb, A compact 0.3-V class AB bulk-driven OTA. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 28(1), 224–232 (2020). https://doi.org/10.1109/TVLSI.2019.2937206

    Article  Google Scholar 

  30. P. Monsurró, S. Pennisi, G. Scotti, A. Trifiletti, Exploiting the body of MOS devices for high performance analog design. IEEE Circuits Syst. Mag. 11(4), 8–23 (2011). https://doi.org/10.1109/MCAS.2011.942751

    Article  Google Scholar 

  31. S. Guo, H. Lee, Dual active-capacitive-feedback compensation for low-power large-capacitive-load three-stage amplifiers. IEEE J. Solid-State Circuits 46(2), 452–464 (2011). https://doi.org/10.1109/JSSC.2010.2092994

    Article  Google Scholar 

  32. M. Akbari, O. Hashemipour, F. Moradi, Input offset estimation of CMOS integrated circuits in weak inversion. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 26(9), 1812–1816 (2018). https://doi.org/10.1109/TVLSI.2018.2830749

    Article  Google Scholar 

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Acknowledgments

This work was supported by the National Natural Science Foundation of China (61804124, 61674122), The Natural Science Project of Shaanxi Province Education Department (18JK0703).

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Authors and Affiliations

  1. School of Electronic Engineering, Xi’an University of Posts & Telecommunications, Xi’an, 710121, China

    Siwan Dong, Xingyuan Tong, Yarong Wang & Cong Liu

  2. Department of Electrical Engineering, Wright State University, Dayton, OH, USA

    Yu Wang

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  1. Siwan Dong
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Correspondence to Siwan Dong.

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Dong, S., Wang, Y., Tong, X. et al. A 0.3-V 8.72-nW OTA with Bulk-Driven Low-Impedance Compensation for Ultra-Low Power Applications. Circuits Syst Signal Process 40, 2209–2227 (2021). https://doi.org/10.1007/s00034-020-01590-9

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