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A New Low-Power Charge Pump with a Glitch-Free PFD for Speedup the Acquisition Process of a PLL in 65 nm CMOS Technology

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Abstract

In this paper, a new low-power charge pump (CP) is presented, which includes a switched-capacitor CP (SC-CP) as the main CP and an auxiliary current-steering CP (ACS-CP) to accelerate the lock process. By using a pulse width controller unit, the ACS-CP activates in predefined phase differences and turns off near the lock region. By utilizing the proposed CP, the issue of traditional current-mismatch error is removed. Also, a new glitch-free phase frequency detector (PFD) with removed reset feedback path to drive the proposed charge pump is presented. Post-layout simulation results in TSMC 65 nm CMOS technology with a 1.2 V supply voltage indicate that the proposed CP consumes 5.4 µW at 125 MHz in the lock state. Also, the proposed PFD illustrates ± 2π detection range and consumes 26.33 µW at 125 MHz. When the proposed CP and PFD are applied to a PLL system, settling time is decreased by more than 50 percent. Also, reference spur at 125 MHz frequency offset and at 8 GHz output frequency is −69 dB. The proposed PFD and CP together occupy an area of 0.0058 mm2.

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Authors and Affiliations

  1. Department of Electrical and Electronic Engineering, Shiraz University of Technology, Shiraz, Iran

    Hossein Ghasemian, Amin Bahrami, Ebrahim Abiri & Mohammad Reza Salehi

  2. Regional Information Center for Science & Technology (RICeST), Jam-E-Jam Ave, Shiraz, Iran

    Mohammad Reza Salehi

Authors
  1. Hossein Ghasemian
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  2. Amin Bahrami
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  3. Ebrahim Abiri
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  4. Mohammad Reza Salehi
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Correspondence to Hossein Ghasemian.

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Ghasemian, H., Bahrami, A., Abiri, E. et al. A New Low-Power Charge Pump with a Glitch-Free PFD for Speedup the Acquisition Process of a PLL in 65 nm CMOS Technology. Circuits Syst Signal Process 40, 2982–3006 (2021). https://doi.org/10.1007/s00034-020-01608-2

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  • DOI: https://doi.org/10.1007/s00034-020-01608-2

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