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A Behavioral SPICE Model of a Binarized Memristor for Digital Logic Implementation

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Abstract

In this paper, a behavioral SPICE memristor model for digital logic implementation is presented and demonstrated in LTSpice. We show binarized state switching and voltage thresholding in the model, which are both important features in practical digital systems. The use of this SPICE model is straightforward and intuitive because almost all parameters in the model can be changed according to the application, including the threshold voltage and the memristance. The LTSpice circuit simulation shows the same characteristics as the original MATLAB numerical implementation, which means that the circuit-level SPICE model can be integrated with other designs. Three types of memristor digital logic circuits are simulated with the LTSpice model with positive results, which proves that the behavioral memristor model has potential application in digital system design.

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The data used to support the findings of this study are available from the corresponding author upon request.

References

  1. J. Borghetti, G.S. Snider, P.J. Kuekes, J.J. Yang, D.R. Stewart, R.S. Williams, ‘Memristive’ switches enable ‘stateful’ logic operations via material implication. Nature 464(7290), 873–876 (2010)

    Article  Google Scholar 

  2. S. Chandrasekaran, F.M. Simanjuntak, R. Saminathan, D. Panda, T.Y. Tseng, Improving linearity by introducing al in hfo2 as a memristor synapse device. Nanotechnology 30(44), 445205 (2019)

    Article  Google Scholar 

  3. L. Chua, Memristor-the missing circuit element. IEEE Trans. Circuit Theory 18(5), 507–519 (1971)

    Article  Google Scholar 

  4. L. Chua, Everything you wish to know about memristors but are afraid to ask. Radioengineering 24(2), 319 (2015)

    Article  Google Scholar 

  5. J.K. Eshraghian, Q. Lin, X. Wang, H.H. Iu, Q. Hu, H. Tong, A behavioral model of digital resistive switching for systems level dnn acceleration. IEEE Trans. Circuits Syst. II Express Briefs 67(5), 956–960 (2020)

    Article  Google Scholar 

  6. M. Khalid, J. Singh, Memristor based unbalanced ternary logic gates. Analog Integr. Circuits Signal Process. 87(3), 399–406 (2016)

    Article  Google Scholar 

  7. S. Kvatinsky, D. Belousov, S. Liman, G. Satat, N. Wald, E.G. Friedman, A. Kolodny, U.C. Weiser, Magic-memristor-aided logic. IEEE Trans. Circuits Syst. II Express Briefs 61(11), 895–899 (2014)

    Article  Google Scholar 

  8. S. Kvatinsky, N. Wald, G. Satat, A. Kolodny, U.C. Weiser, E.G. Friedman, Mrl–memristor ratioed logic, in: 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications, pp. 1–6. IEEE (2012)

  9. Z. Lin, Y. Wang, C. Peng, W. Lu, X. Li, X. Wu, J. Chen, Read-decoupled 8t1r non-volatile sram with dual-mode option and high restore yield. Electron. Lett. 55(9), 519–521 (2019)

    Article  Google Scholar 

  10. F. Meng, X. Zeng, Z. Wang, Impulsive anti-synchronization control for fractional-order chaotic circuit with memristor. Indian J. Phys. 93(9), 1187–1194 (2019)

    Article  Google Scholar 

  11. D.B. Strukov, G.S. Snider, D.R. Stewart, R.S. Williams, The missing memristor found. Nature 453(7191), 80–83 (2008)

    Article  Google Scholar 

  12. N. Talati, S. Gupta, P. Mane, S. Kvatinsky, Logic design within memristive memories using memristor-aided logic (magic). IEEE Trans. Nanotechnol. 15(4), 635–650 (2016)

    Article  Google Scholar 

  13. X. Wang, X. Min, P. Zhou, D. Yu, Hyperchaotic circuit based on memristor feedback with multistability and symmetries. Complexity 2020, 2620375 (2020). https://doi.org/10.1155/2020/2620375

    Article  Google Scholar 

  14. X. Wang, J. Yu, C. Jin, H.H.C. Iu, S. Yu, Chaotic oscillator based on memcapacitor and meminductor. Nonlinear Dyn. 96(1), 161–173 (2019)

    Article  Google Scholar 

  15. X.Y. Wang, P.F. Zhou, J.K. Eshraghian, C.Y. Lin, H.H.C. Iu, T.C. Chang, S.M. Kang, High-density memristor-cmos ternary logic family. IEEE Trans. Circuits Syst. I Regul. Pap. (2020)

  16. B. Zhao, M. Xiao, Y.N. Zhou, Synaptic learning behavior of a TiO\(_2\) nanowire memristor. Nanotechnology 30(42), 425202 (2019)

    Article  Google Scholar 

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Acknowledgements

This work was supported by the National Natural Science Foundation of China (Grant No. 61871429), and the Natural Science Foundation of Zhejiang Province (Grant No. LY18F010012).

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Correspondence to Xiaoyuan Wang or Congying Ha.

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Wang, X., Jin, C., Eshraghian, J.K. et al. A Behavioral SPICE Model of a Binarized Memristor for Digital Logic Implementation. Circuits Syst Signal Process 40, 2682–2693 (2021). https://doi.org/10.1007/s00034-020-01611-7

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