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DGFinSAL: A New Low Power Adiabatic FinFET-Based Logic Family for DPA-Resistant Applications

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Abstract

In this paper, a novel low power, adiabatic, DPA-resistant logic family based on double-gate FinFET transistors is presented. Internet-of-Things devices have gained many applications in all aspects of human life. Therefore, the security and energy efficiency of such device is very important. Radio-frequency identification tags and wireless sensor networks use AES modules to encrypt secret information. Attackers have successfully tampered these modules using differential power analysis (DPA) attacks. Therefore, DPA-resistant circuits with high immunity are desirable. The proposed logic circuit family has been simulated using HSPICE and PTM 20 nm technology parameters. Simulation results show that the proposed logic circuits consume lower power up to 40% in comparison with the previous designs. Furthermore, the security of the proposed logic is evaluated using an 8-bit SBOX as a test bench circuit. It has been shown that the proposed design is immune to a DPA, through simulated attacks using Cadence Virtuoso and MATLAB software.

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Data availability

The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.

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Authors and Affiliations

  1. Faculty of Electrical Engineering, Shahid Beheshti University, Tehran, Iran

    Ehsan Panahifar & Alireza Hassanzadeh

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  1. Ehsan Panahifar
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  2. Alireza Hassanzadeh
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Correspondence to Alireza Hassanzadeh.

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Panahifar, E., Hassanzadeh, A. DGFinSAL: A New Low Power Adiabatic FinFET-Based Logic Family for DPA-Resistant Applications. Circuits Syst Signal Process 40, 4877–4902 (2021). https://doi.org/10.1007/s00034-021-01696-8

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