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Design of Memristor-Based Combinational Logic Circuits

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Abstract

This paper proposes three modified memristor ratioed logic (MRL) gates: NOT, NOR and A AND (NOR B) (i.e., \(A \cdot \bar{B}\)), each of which only needs 1 memristor and 1 NMOS. Based on the modified MRL gates, we design some combinational logic circuits, including 1-bit comparator, 3-bit binary encoder, 3-bit binary decoder and 4:1 multiplexer. Furthermore, an improved multifunctional logic module is proposed, which contains one NMOS transistor and five memristors, and can implement AND, OR and XOR logic operations. Using this multifunctional logic module, a 4-bit comparator and a 1-bit full adder are designed. Finally, the proposed combinational logic circuits are verified by LTSPICE simulations. Compared with other memristor-based logic circuits and the traditional CMOS technology, the proposed logic circuits have made great progress in reducing delay, power consumption and the number of transistors.

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Data Availability

The authors first thank the anonymous reviewers, and the datasets generated during the current study are available from the corresponding author on reasonable request.

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Acknowledgements

This work was supported by the National Natural Science Foundation of China (Grant Nos. 61771176, 61801154, 61271064).

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Authors and Affiliations

  1. Institute of Modern Circuits and Intelligent Information, Hangzhou Dianzi University, Hangzhou, 310018, China

    Gongzhi Liu, Shuhang Shen, Peipei Jin, Guangyi Wang & Yan Liang

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  1. Gongzhi Liu
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  2. Shuhang Shen
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  3. Peipei Jin
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  4. Guangyi Wang
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  5. Yan Liang
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Correspondence to Guangyi Wang.

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Liu, G., Shen, S., Jin, P. et al. Design of Memristor-Based Combinational Logic Circuits. Circuits Syst Signal Process 40, 5825–5846 (2021). https://doi.org/10.1007/s00034-021-01770-1

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