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Low-Complex and Low-Power n-dimensional Gram–Schmidt Orthogonalization Architecture Design Methodology

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Abstract

Gram–Schmidt orthogonalization is a popular fundamental technique of linear algebra, having wide-spread applications in state-of-the art and next-generation signal processing and communication technologies including Blind Source Separation, Independent Component Analysis, MIMO technology, Orthogonal Frequency Division Multiplexing, and QR Decomposition. On the other hand, Coordinate Rotation Digital Computer (CORDIC) is a technique being extensively used for the efficient implementation of complex arithmetic operations in various signal processing and communication modules. For all the aforementioned applications including FastICA and QR decomposition, CORDIC is being used widely for all the modules except GS where still costly multipliers, dividers, square root, and addition operations are being used. It motivated us to investigate the design for GS using CORDIC resulting in low-power and low-complex architecture of the entire design. In this paper, we propose a CORDIC-based low-complexity, low-power architecture design methodology for the n-dimensional GS algorithm where a single CORDIC unit can be re-used for implementation of several processing and communication modules on-chip. The proposed architecture precludes the use of additional arithmetic units to perform costly operations by recursive use of CORDIC, and thus significantly reduces its hardware complexity. The proposed architecture reduces the power consumption by 74–86\(\%\) and the area by 12–40\(\%\) for 3D to 6D GS, respectively, over the conventional approach.

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Acknowledgements

This work is partially supported by Ministry of Electronics and Information Technology (Govt of India) funded “Indigenous Intelligent and Scalable Neuromorphic Multi Chip for AI Training and Inference Solutions” project dated March 2021. CAD Tools are supported under MeitY SMDPC2S Program, Government of India.

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Authors and Affiliations

  1. Electrical Engineering Department in the Indian Institute of Technology, Hyderabad, India

    Swati Bhardwaj, Shashank Raghuraman & Amit Acharyya

  2. Electrical Engineering in the Stanford University, Stanford, USA

    Jayesh B. Yerrapragada

  3. Nanyang Technological University, Singapore, Singapore

    Agathya Jagirdar

  4. School of Electronics and Computer Science, University of Southampton, Southampton, UK

    Koushik Maharatna

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  1. Swati Bhardwaj
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  2. Shashank Raghuraman
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  3. Jayesh B. Yerrapragada
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  5. Koushik Maharatna
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  6. Amit Acharyya
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Correspondence to Amit Acharyya.

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Bhardwaj, S., Raghuraman, S., Yerrapragada, J.B. et al. Low-Complex and Low-Power n-dimensional Gram–Schmidt Orthogonalization Architecture Design Methodology. Circuits Syst Signal Process 41, 1633–1659 (2022). https://doi.org/10.1007/s00034-021-01852-0

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