Skip to main content
SpringerLink
Log in

Low-Power and Fast-Swing-Restoration GDI-Based Magnitude Comparator for Digital Images Processing

  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

A new 1-bit digital comparator named 14T-SR-GDI is presented with gate-diffusion-input (GDI) and single-swing-restoration (SR) techniques to attain internal gates with high driving capability. The comparator has 14 transistors which produce full-swing outputs with low power consumption. In the 14T-SR-GDI, boosted inner signals are used to activate the output gates which result in a high-speed circuit with effective scalability and the enhanced driving capability for multi-bit structures. The comparator has a low power delay product (PDP) due to the small numbers of internal nodes and capacitances and efficient power-ground-free gates. The 14T-SR-GDI comparator, fully SR-GDI-based AND, and OR gates, construct a new tree structure for multi-bit magnitude comparators including 2-bit, 4-bit, 8-bit, and 16-bit comparators. The proposed 1-bit comparator is used in image processing for difference detection, and its efficiency is proved by image quality parameters. The post-layout simulations are performed for the 1-bit to 16-bit structures under TSMC 90 nm technology. The extracted results express a PDP with an average difference of 9.59% between the regular and post-layout modes. Also, the proposed 16-bit comparator is embedded in a pad with a total area of 4331.25 μm2. The designed magnitude comparators are key components in digital signal processors (DSPs).

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15

Similar content being viewed by others

Data availability

The datasets generated during the current study are available from the corresponding author on reasonable request.

References

  1. E. Abiri, A. Darabi, M.R. Salehi, A. Sadeghi, Optimized gate diffusion input method-based reversible magnitude arithmetic unit using non-dominated sorting genetic algorithm II. Circuits Syst. Signal Process. 39, 4516–4551 (2020). https://doi.org/10.1007/s00034-020-01382-1

    Article  Google Scholar 

  2. M. Aggarwal, R. Mehra, Performance analysis of magnitude comparator using different design techniques. Int. J. Comput. Appl. 115(14), 12–15 (2015). https://doi.org/10.5120/20218-2496

    Article  Google Scholar 

  3. M. Aguirre-Hernandez, M. Linares-Aranda, CMOS full-adders for energy-efficient arithmetic applications. IEEE Trans Very Large Scale Integr. (VLSI) Syst. 19(4), 718–721 (2011). https://doi.org/10.1109/TVLSI.2009.2038166

    Article  Google Scholar 

  4. M. Ahmadinejad, M. Hossein Moaiyeri, F. Sabetzadeh, Energy and area efficient imprecise compressors for approximate multiplication at nanoscale. Int. J. Electron. Commun. 110, 152859 (2019). https://doi.org/10.1016/j.aeue.2019.152859

    Article  Google Scholar 

  5. S. Alam, S.R. Ghimiray, M. Kumar. Performance analysis of a 4-bit comparator circuit using different adiabatic logics, in Innovations in Power and Advanced Computing Technologies (i-PACT), Vellore (2017), pp. 1–5. https://doi.org/10.1109/IPACT.2017.8245210

  6. M. Basha, V.N. Lakshmana Kumar, Transistor implementation of reversible comparator circuit using low power technique. IJCSIT Int. J. Comput. Sci. Inf. Technol. 3(3), 4447–4452 (2012)

    Google Scholar 

  7. H. Basireddy, K. Challa, T. Nikoubin, Hybrid logical effort for hybrid logic style full adders in multistage structures. IEEE Trans. Very Large Scale Integr. Syst. 27(5), 1138–1147 (2019)

    Article  Google Scholar 

  8. F. Behbahani, M.K.Q. Jooq, M.H. Moaiyeri, K. Tamersit, Leveraging negative capacitance CNTFETs for image processing: an ultra-efficient ternary image edge detection hardware. IEEE Trans. Circuits Syst. I Regul. Pap. 68(12), 5108–5119 (2021). https://doi.org/10.1109/TCSI.2021.3112798

    Article  Google Scholar 

  9. M.H. Ben-Jamaa, K. Mohanram, G. De Micheli, An efficient gate library for ambipolar CNTFET logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(2), 242–255 (2011). https://doi.org/10.1109/TCAD.2010.2085250

    Article  Google Scholar 

  10. B.H. Calhoun, A. Wang, A. Chandrakasan, Modeling and sizing for minimum energy operation in subthreshold circuits. IEEE J. Solid-State Circuits 40(9), 1778–1786 (2005)

    Article  Google Scholar 

  11. S.W. Cheng. A high-speed magnitude comparator with small transistor count, in 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS. Proceedings of the 2003, Sharjah (2003), pp. 1168–1171. https://doi.org/10.1109/ICECS.2003.1301720

  12. P. Chuang, D. Li, M. Sachdev, A low-power high-performance single-cycle tree-based 64-bit binary comparator. IEEE Trans. Circuits Syst. II Express Briefs 59(2), 108–112 (2012). https://doi.org/10.1109/TCSII.2011.2180110

    Article  Google Scholar 

  13. H.M. Gaur, A.K. Singh, U. Ghanekar, In-depth comparative analysis of reversible gates for designing logic circuits. Procedia Comput. Sci. 125, 810–817 (2018). https://doi.org/10.1016/j.procs.2017.12.103

    Article  Google Scholar 

  14. C.-H. Huang, JSh. Wang, High-performance and power-efficient CMOS comparators. IEEE J. Solid-State Circuits 38(2), 254–262 (2003). https://doi.org/10.1109/JSSC.2002.807409

    Article  Google Scholar 

  15. H. Jayashree, H. Thapliyal, H. Arabnia, V.K. Agrawal, Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier. J. Supercomput. 72, 1477–1493 (2016). https://doi.org/10.1007/s11227-016-1676-0

    Article  Google Scholar 

  16. A. Kabbani, Logical effort based dynamic power estimation and optimization of static CMOS circuits. Integr. VLSI J. 43(3), 279–288 (2010)

    Article  Google Scholar 

  17. J. Kandpal, A. Tomar, M. Agarwal, K.K. Sharma, High-speed hybrid-logic full adder using high-performance 10-T XOR–XNOR cell. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 28(6), 1413–1422 (2020). https://doi.org/10.1109/TVLSI.2020.2983850

    Article  Google Scholar 

  18. F. Knoll et al., fastMRI: a publicly available raw k-space and DICOM dataset of knee images for accelerated MR image reconstruction using machine learning. Radiol. Artif. Intell. 2(1), e190007 (2020). https://doi.org/10.1148/ryai.2020190007

    Article  Google Scholar 

  19. M. Lustig, D.L. Donoho, J.M. Santos, J.M. Pauly, Compressed sensing MRI. IEEE Signal. Process. Mag. 25(2), 72–82 (2008)

    Article  Google Scholar 

  20. A. Momeni, J. Han, P. Montuschi, F. Lombardi, Design and analysis of approximate compressors for multiplication. IEEE Trans. Comput. 64(4), 984–994 (2015). https://doi.org/10.1109/TC.2014.2308214

    Article  MathSciNet  MATH  Google Scholar 

  21. M. Monajati, S.M. Fakhraie, E. Kabir, Approximate arithmetic for low-power image median filtering. Circuits Syst. Signal Process. 34, 3191–3219 (2015). https://doi.org/10.1007/s00034-015-9997-4

    Article  Google Scholar 

  22. A. Morgenshtein, A. Fish, I. Wagner, Gate diffusion input (GDI): a power-efficient method for digital combinatorial circuits. IEEE Trans Very Large Scale Integr. (VLSI) Syst. 10, 566–581 (2002). https://doi.org/10.1109/TVLSI.2002.801578

    Article  Google Scholar 

  23. A. Morgenshtein, V. Yuzhaninov, A. Kovshilovsky, A. Fish, Full-swing gate diffusion input logic—case-study of low-power CLA adder design. Integr. VLSI J. 47, 62–70 (2014). https://doi.org/10.1016/j.vlsi.2013.04.002

    Article  Google Scholar 

  24. K. Morita. Chapter 4, Reversible logic gates,. in Theory of Reversible Computing. Monographs in Theoretical Computer Science. An EATCS Series (Springer, Tokyo, 2017)

  25. A. Moustafa, A. Younes, Efficient synthesis of reversible circuits using quantum dot cellular automata. IEEE Access 9, 76662–76673 (2021). https://doi.org/10.1109/ACCESS.2021.3083507

    Article  Google Scholar 

  26. M.J. Muckley et al., Results of the 2020 fastMRI challenge for machine learning MR image reconstruction. IEEE Trans. Med. Imaging 40(9), 2306–2317 (2021). https://doi.org/10.1109/TMI.2021.3075856

    Article  Google Scholar 

  27. D.N. Mukherjee, S. Panda, B. Maji. Design of low power 12-bit magnitude comparator, in Devices for Integrated Circuit (DevIC) (2017), pp. 103–109. https://doi.org/10.1109/DEVIC.2017.8073916

  28. M. Nabavi, F. Ramezankhani, M. Shams, Optimum pMOS-to-nMOS width ratio for efficient subthreshold CMOS circuits. IEEE Trans. Electron Devices 63(3), 916–924 (2016). https://doi.org/10.1109/TED.2016.2517446

    Article  Google Scholar 

  29. H. Naseri, S. Timarchi, Low-power and fast full adder by exploring new XOR and XNOR gates. IEEE Trans. Very Large Scale Integration (VLSI) Syst. 26(8), 1481–1493 (2018). https://doi.org/10.1109/TVLSI.2018.2820999

    Article  Google Scholar 

  30. T. Nikoubin, M. Grailoo, C. Li, Energy and area efficient three-input XOR/XNORs with systematic cell design methodology. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24(1), 398–402 (2016). https://doi.org/10.1109/TVLSI.2015.2393717

    Article  Google Scholar 

  31. S. Raveendran, P.J. Edavoor, N.Y.B. Kumar, M.H. Vasantha, An approximate low-power lifting scheme using reversible logic. IEEE Access 8, 183367–183377 (2020). https://doi.org/10.1109/ACCESS.2020.3029149

    Article  Google Scholar 

  32. A. Sadeghi, N. Shiri, M. Rafiee, High-efficient, ultra-low-power and high-speed 4:2 compressor with a new full adder cell for bioelectronics applications. Circuits Syst. Signal Process. (2020). https://doi.org/10.1007/s00034-020-01459-x

    Article  Google Scholar 

  33. Y. Safaei-Mehrabani, M. Eshghi, Noise and process variation tolerant, low-power, high-speed, and low-energy full adders in CNFET technology. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24(11), 3268–3281 (2016). https://doi.org/10.1109/TVLSI.2016.2540071

    Article  Google Scholar 

  34. Y. Safaei-Mehrabani, R. Faghih-Mirzaee, Z. Zareei, S.M. Daryabari, A novel high-speed, low-power CNTFET-based inexact full adder cell for image processing application of motion detector. J. Circuits Syst. Comput. 26(5), 17500821–15 (2017). https://doi.org/10.1142/S0218126617500827

    Article  Google Scholar 

  35. S. Sayyah, M. Hossein Moaiyeri, M. Moghaddam, Sh. Hessabi, A low-power single-ended SRAM in FinFET technology. AEU Int. J. Electron. Commun. 99, 361–368 (2018). https://doi.org/10.1016/j.aeue.2018.12.015

    Article  Google Scholar 

  36. G. Sharma, H. Arora, J. Chawla, J. Ramzai. Comparative analysis of a 2-bit magnitude comparator using various high performance techniques, in International Conference on Communications and Signal Processing (ICCSP), Melmaruvathur (2015), pp. 0079–0083. https://doi.org/10.1109/ICCSP.2015.7322602

  37. V. Shekhawat, T. Sharma, K.G. Sharma. 2-Bit magnitude comparator using GDI technique, in International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2014), Jaipur (2014), pp. 1–5. https://doi.org/10.1109/ICRAIE.2014.6909270

  38. V.V. Shende, A.K. Prasad, I.L. Markov, J.P. Hayes, Synthesis of reversible logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6), 710–722 (2003). https://doi.org/10.1109/TCAD.2003.811448

    Article  Google Scholar 

  39. D.K. Sodickson, W.J. Manning, Simultaneous acquisition of spatial harmonics (SMASH): fast imaging with radiofrequency coil arrays. Magn. Res. Med. 38(4), 591–603 (1997)

    Article  Google Scholar 

  40. N.H. Strickland, PACS (picture archiving and communication systems): filmless radiology. Arch. Dis. Childhood 83, 82–86 (2000). https://doi.org/10.1136/adc.83.1.82

    Article  Google Scholar 

  41. A.G.M. Strollo, E. Napoli, D. De Caro, N. Petra, G.D. Meo, Comparison and extension of approximate 42 compressors for low-power approximate multipliers. IEEE Trans. Circuits Syst. I Regul. Pap. (2020). https://doi.org/10.1109/TCSI.2020.2988353

    Article  MATH  Google Scholar 

  42. M. Takbiri, R. Faghih Mirzaee, K. Navi, Analytical review of noise margin in MVL: clarification of a deceptive matter. Circuits Syst. Signal Process. 38, 4280–4301 (2019)

    Article  Google Scholar 

  43. S.D. Thabah, P. Saha, New design approaches of reversible BCD encoder using Peres and Feynman gates. ICT Express J. 6(1), 38–42 (2020). https://doi.org/10.1016/j.icte.2019.07.001

    Article  Google Scholar 

  44. S. Tripathy, S.K. Mandal, BSh. Patro, L.B. Omprakash, Low power, high speed 8-bit magnitude comparator in 45nm technology for signal processing application. Indian J. Sci. Technol. 9, 1–10 (2015)

    Article  Google Scholar 

  45. C. Wang, C. Wu, K. Tsai, 1 GHz 64-bit high-speed comparator using ANT dynamic logic with two-phase clocking. IEEE Proc. Comput. Digit. Tech. 145(6), 433–436 (1998). https://doi.org/10.1049/ip-cdt:19982348

    Article  Google Scholar 

  46. N. Weste, D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th edn. (Pearson, 2010)

    Google Scholar 

  47. https://www.gehealthcare.com/courses/xeleris-workstation

Download references

Author information

Authors and Affiliations

  1. Department of Electrical Engineering, Shiraz Branch, Islamic Azad University, Shiraz, Iran

    Mahmood Rafiee, Nabiollah Shiri & Ayoub Sadeghi

  2. Department of Electrical and Electronics Engineering, Shiraz University of Technology, Modarres Blvd, Shiraz, Iran

    Abdolreza Darabi & Ebrahim Abiri

Authors
  1. Mahmood Rafiee
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Nabiollah Shiri
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Ayoub Sadeghi
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Abdolreza Darabi
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Ebrahim Abiri
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Nabiollah Shiri.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Rafiee, M., Shiri, N., Sadeghi, A. et al. Low-Power and Fast-Swing-Restoration GDI-Based Magnitude Comparator for Digital Images Processing. Circuits Syst Signal Process 41, 4848–4885 (2022). https://doi.org/10.1007/s00034-022-01997-6

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-022-01997-6

Keywords

Search

Navigation