Abstract
To solve large number of digital signal processing problems, such as on-board radar-location or hydro-acoustic systems, it is necessary to perform discrete trigonometric transforms over intensive data flows in real time with the constraints on size and power consumption. To solve this problem, the hardware implementation in the form of the VLSI has been proposed. In particular, we improve an algorithm for the fast cosine and sine Fourier transforms with a focus on the parallel-streaming hardware implementation. A flow graph of the improved algorithm has been developed on the basis of addition, subtraction and multiplication of real numbers with the relation scheme of algorithms. A linear projection of the improved algorithm for fast cosine and sine Fourier transforms on the axis parallel to the data transmission has been obtained. This makes it possible to change the type and dimensions of the transforms. Further, we develop a structure of 2-4-8-16-point processor for fast cosine and sine Fourier transforms. Such an implementation provides a reduction of the dimensions, energy consumption and performance of the transforms in real time.















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Tsmots, I., Rabyk, V., Kryvinska, N. et al. Design of the Processors for Fast Cosine and Sine Fourier Transforms. Circuits Syst Signal Process 41, 4928–4951 (2022). https://doi.org/10.1007/s00034-022-02012-8
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DOI: https://doi.org/10.1007/s00034-022-02012-8