Skip to main content
SpringerLink
Log in

Design of the Processors for Fast Cosine and Sine Fourier Transforms

  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

To solve large number of digital signal processing problems, such as on-board radar-location or hydro-acoustic systems, it is necessary to perform discrete trigonometric transforms over intensive data flows in real time with the constraints on size and power consumption. To solve this problem, the hardware implementation in the form of the VLSI has been proposed. In particular, we improve an algorithm for the fast cosine and sine Fourier transforms with a focus on the parallel-streaming hardware implementation. A flow graph of the improved algorithm has been developed on the basis of addition, subtraction and multiplication of real numbers with the relation scheme of algorithms. A linear projection of the improved algorithm for fast cosine and sine Fourier transforms on the axis parallel to the data transmission has been obtained. This makes it possible to change the type and dimensions of the transforms. Further, we develop a structure of 2-4-8-16-point processor for fast cosine and sine Fourier transforms. Such an implementation provides a reduction of the dimensions, energy consumption and performance of the transforms in real time.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15

Similar content being viewed by others

Data availability

Our manuscript has no associated data.

References

  1. N. Ahmed, T. Natarajan, K.R. Rao, Discrete cosine transform. IEEE Trans. Comput. 23, 90–93 (1974)

    Article  MathSciNet  Google Scholar 

  2. A. Batyuk, E. Struk, I. Tsmots, Development principles and criteria for the selection of VLSI-structures for coordinated parallel calculation of basic operations of real-time digital signal processing algorithms, in Proceedings of the 9th International Conference on The Experience of Designing and Application of CAD Systems in Microelectronics, CADSM 2007, Lviv-Polyana, Ukraine, 19–24 Feb. 2007, pp. 179–180.

  3. R.E. Blahut, Fast algorithms for signal processing. 1ed. Cambridge University Press: New York, USA, 2010

  4. N. Brisebarre, M. Joldeş, J.-M. Muller, A.-M. Naneş, J. Picot, Error analysis of some operations involved in the cooley-Tukey fast fourier transform. ACM Trans. Math. Soft. 46(2), 1–27 (2020)

    Article  MathSciNet  Google Scholar 

  5. W. Chen, C. Smith, S. Fralick, A fast computational algorithm for the discrete cosine transform. IEEE Trans. Commun. 25(9), 1004–1009 (1977)

    Article  Google Scholar 

  6. J.W. Cooley, J.W. Tukey, An algorithm for machine calculation of complex Fourier series. Math. Comput. 19, 297–301 (1965)

    Article  MathSciNet  Google Scholar 

  7. P. Duhamel, M. Vitterli, Fast Fourier transform: a tutorial review and a state of the art. Signal Process. 19, 259–299 (1990)

    Article  MathSciNet  Google Scholar 

  8. Electronic components database. Available online: https://www.digchip.com/datasheets/parts/datasheet/033/EP3C16F484C6.php. Accessed 5 Aug 2020.

  9. M. Garrido, J. Grajal, M.A. Sanchez, O. Gustafsson, Pipelined radix-2k feedforward FFT architectures. IEEE Trans Very Large Scale Integr. Syst. 21, 23–32 (2011)

    Article  Google Scholar 

  10. M. Garrido, S. Huang, S. Chen, O. Gustafsson, The serial commutator FFT. IEEE Trans. Circuits Syst. II Express Briefs 63(10), 974–978 (2016)

    Article  Google Scholar 

  11. L.O. Hnativ, Integer cosine transforms for high-efficiency image and video coding. Cybern. Syst. Anal. 52(5), 802–816 (2016)

    Article  MathSciNet  Google Scholar 

  12. C. Ingemarsson, P. Källström, F. Qureshi, O. Gustafsson, Efficient FPGA Mapping of Pipeline. IEEE Trans. Very Large Scale Integr. Syst. 25, 2486–2497 (2017)

    Article  Google Scholar 

  13. K.J. Jones, R. Coster, Area-efficient and scalable solution to real-data fast fourier transform via regularised fast Hartley transform. IET Signal Proc. 1(3), 128–138 (2007)

    Article  Google Scholar 

  14. M. Kasyanchuk, I. Yakymenko, S. Ivas’ev, Ya. Nykolaychuk, Fundamental theoretical and algorithmic principles of the applied tasks decision of theory of numbers and construction of the high-performance special processors on their basis, in Proceedings of the XI International Conference on The Experience of Designing and Application of CAD Systems in Microelectronics, CADSM 2011, 23–25 February, 2011, Polyana-Svalyava (Zakarpattya), Ukraine, pp.168–169 (2011).

  15. V. Kumar, K.K. Mahapatra, et al. An efficient distributed arithmetic based VLSI architecture for DCT. IEEE Trans. Circ. Syst. I Regular Papers, pp. 978–983 (2011).

  16. A.C. Mert, E. Kalali, I. Hamzaoglu, High performance 2D transform hardware for future video coding. IEEE Trans. Consum. Electron. 63(2), 117–125 (2017)

    Article  Google Scholar 

  17. J.G. Nash, Distributed-memory-based FFT architecture and FPGA implementations. Electronics 7, 116 (2018)

    Article  Google Scholar 

  18. A. Nukada, Y. Maruyama, S. Matsuoka, High performance 3-D FFT using multiple CUDA GPUs, in Proceedings of the 5th Annual Workshop on General Purpose Processing with Graphics Processing Units, GPGPU-5, New York, NY, USA, ACM, , pp. 57–63 (2012).

  19. OBrien Labs. Altera Cyclone II, III, IV Development Kits. Available online: https://obrienlabs.blogspot.com/2010/12/altera-cyclone-iii-development-kits.html. (accessed on 05.08.2020).

  20. I. Prots’ko, V. Teslyuk, Algorithm of efficient computation DSTI-IV using cyclic convolutions. WSEAS Trans. Signal Process. 10, 278–288 (2014)

    Google Scholar 

  21. I. Prots’ko, Algorithm of efficient computation of generalised discrete Hartley transform based on cyclic convolutions. IET Signal Proc. 4(8), 301–308 (2014)

    Article  Google Scholar 

  22. D. Puchala, K. Stokfiszewski, B. Szczepaniak, M. Yatsymirskyy, Effectiveness of Fast Fourier Transform implementations on GPU and CPU. Przeglad Elektrotechniczny 92(7), 69–71 (2016)

    Google Scholar 

  23. M. Raguraman, D. Saravanan, FPGA implementation of approximate 2d discrete cosine transforms. Circuits Syst. 7, 434–445 (2016)

    Article  Google Scholar 

  24. K.R. Rao, D.N. Kim, J.J. Hwang, Fast Fourier Transform—Algorithms and Applications (Springer, Berlin, 2011)

    MATH  Google Scholar 

  25. B.R. Rau, J.A. Fisher, Instruction-level parallel processing: history, overview and perspective. J. Supercomput. 7(1), 9–50 (1993)

    Article  Google Scholar 

  26. J.J. Rodriguez-Andina, M.J. Moure, M.D. Valdes-Pena, Advanced features and industrial applications of FPGAs—a review. IEEE Trans. Ind. Inform. 11, 853–864 (2015)

    Article  Google Scholar 

  27. P. Saha, A. Banerjee, A. Dandapat, P. Bhattacharyya, ASIC implementation of high speed processor for calculating discrete Fourier transformation using circular convolution technique. WSEAS Trans. Circuits Syst. 10, 278–288 (2011)

    Google Scholar 

  28. S. Shen, W. Shen, Y. Fan, X. Zeng, A Unified 4/8/16/32-Point Integer IDCT architecture for multiple video coding standards, in IEEE International Conference on Multimedia and Expo, ICME, Melbourne, VIC Australia, 9-13, pp. 788–793 (2012)

  29. G. Sohi, Instruction issue logic for high-performance interruptible, multiple functional unit, pipelined computers. IEEE Trans. Comput. 39(3), 349–359 (1990)

    Article  Google Scholar 

  30. K. Stokfiszewski, K. Wieloch, M. Yatsymirskyy, The fast fourier transform partitioning scheme for GPU’s computation effectiveness improvement, in Advances in Intelligent Systems and Computing, Springer: Lviv, Ukraine, 2018, Volume 689, pp. 511–522 (2018).

  31. T.-Y. Sung, Y.-S. Shieh, An efficient VLSI linear array for DCT/IDCT using subband decomposition algorithm. Hindawi Publishing Corporation Mathematical Problems in Engineering, 2010, 87–93.

  32. T. Tao, S. Liu, H. Ma, M. Li, X. Zhou, X. Wang, J. Weng, Twiddle factor neutralization method for heterodyne velocimetry. Rev. Sci. Instrum. 85(1), 013101 (2014). https://doi.org/10.1063/1.4859598

    Article  Google Scholar 

  33. Terasic Technologies FPGA Dev Kits for Altera Cyclone® II, III, & IV. Available online: https://ru.mouser.com/new/terasic-technologies/terasic-fpga-dev-cyclone-kits/ (accessed on 05.08.2020).

  34. R.L. Tokheim, Digital Electronics: Principles and Application. 8th edition. McGraw Hill Higher Education: New York, USA, January 16, 576 (2013).

  35. I.G. Tsmots, Informatsijni tehnologii ta spetsializovani zasoby obrobky sygnaliv i zobrazhen u realnomu chasi. UAD: Lviv, Ukraine, (2005). (in Ukrainian).

  36. J. Wu, Jaja, j. High Performance FFT Based Poisson Solver on a CPU-GPU Heterogeneous Platform. Processing (IPDPS) 2013 IEEE 27th International Symposium on Parallel & Distributed, Boston, MA, USA, 20–24 May 2013, pp. 115–125.

  37. M.M. Yatsymirskyy, Shvydki algorytmy ortogonalnyh trygonometrychnyh peretvoren. Akademichnyj Expres: Lviv, Ukraine, (1997). (in Ukrainian).

  38. Md. ZainulAbidin, M.O. Sharrif, Tan shao theong design of a VLSI digit slicing fast Fourier transform processor. Microelectron. J. 22(5–6), 15–26 (1991)

    Google Scholar 

  39. X. Zhao, J. Chen, M. Karczewicz, L. Zhang, X. Li, W. Chien, Enhanced multiple transform for video coding, in Proceedings on data compression conference, Snowbird, UT, USA, pp. 73–82 (2016).

Download references

Author information

Authors and Affiliations

  1. Department of Automated Control Systems, Lviv Polytechnic National University, Lviv, 79013, Ukraine

    Ivan Tsmots & Vasyl Teslyuk

  2. Department of RadioPhysics and Computer Technologies, Ivan Franko National University of Lviv, 1, Universytetska Str., Lviv, 79000, Ukraine

    Vasyl Rabyk

  3. Department of Information Systems, Faculty of Management, Comenius University, Bratislava, Bratislava, 25 82005, Slovakia

    Natalia Kryvinska

  4. Institute of Information Technology, Lodz University of Technology, Wolczanska 215 Street, Lodz, Poland

    Natalia Kryvinska & Mykhaylo Yatsymirskyy

Authors
  1. Ivan Tsmots
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Vasyl Rabyk
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Natalia Kryvinska
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Mykhaylo Yatsymirskyy
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Vasyl Teslyuk
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding authors

Correspondence to Natalia Kryvinska or Vasyl Teslyuk.

Ethics declarations

Conflict of interest

The authors declare that they have no conflict of interest/competing interests.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Tsmots, I., Rabyk, V., Kryvinska, N. et al. Design of the Processors for Fast Cosine and Sine Fourier Transforms. Circuits Syst Signal Process 41, 4928–4951 (2022). https://doi.org/10.1007/s00034-022-02012-8

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-022-02012-8

Keywords

Search

Navigation