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An FPGA Implementation of an Impulse Noise Reduction Algorithm in Visual Sensor Network

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Abstract

In this paper, nearest neighbor filtering method is presented for impulse noise reduction. If a pixel is corrupted by impulse noise, nearest non-noisy pixel can be a better option to replace it. The algorithm is implemented on Zynq ZCU104 field programmable gate array board. The resource requirements are approximately 12 and 20 times lesser in comparison with low-latency median filter and pipelined median filter architecture hardware implementations, respectively. Also the reconstructed image quality is better in comparison with the state-of-the-art denoising methods for noise densities above 20%. The presented architecture is able to denoise 271 high definition (720p) images per second. This makes the presented method a better choice to be used in memory and resource constrained visual sensor network devices.

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Data Availability

The MATLAB code files for this paper is available at https://github.com/rafimiet/NNFM.git and the VHDL code files are available at https://github.com/rafimiet/NNFM_VHDL.git.

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Lone, M.R. An FPGA Implementation of an Impulse Noise Reduction Algorithm in Visual Sensor Network. Circuits Syst Signal Process 41, 6136–6151 (2022). https://doi.org/10.1007/s00034-022-02069-5

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