Abstract
In this paper, an improved harmonic rejecting N-path filter with a circuit-level structure is proposed. A different set of mixing functions is introduced to conventional N-path filters. Systematic analysis shows that the mixing functions have the benefits of harmonic rejection at the radio frequency node. An 8-path circuit-level structure is proposed, and a harmonic gain calibration technique is introduced to calibrate the errors due to the process variation and mismatch. The proposed 8-path filter is designed and simulated under the 65-nm CMOS technology and achieves 17–\(29\,\hbox {dB}\) gain with a \(2\mathrm{nd}\) harmonic rejection ratio of 24–\(31\,\hbox {dB}\), \(3\mathrm{rd}\)–\(6\mathrm{th}\) harmonic rejection ratio of 35–\(60\,\hbox {dB}\), a frequency range of 0.1–\(1\hbox {GHz}\), and a noise figure of 3.8–\(4.9\,\hbox {dB}.\)
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Acknowledgements
We would like to thank the Natural Science Foundation of Shanghai (20ZR1425900) and Shanghai Aerospace Advanced Technology Joint Research Fund (USCAST2020-30) for funding this research.
Funding
This study was funded by Natural Science Foundation of Shanghai (20ZR1425900) and Shanghai Aerospace Advanced Technology Joint Research Fund (USCAST2020-30).
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Bu, R., Jin, J., Yang, Z. et al. A Harmonic Rejecting N-Path Filter with Harmonic Gain Calibration Technique. Circuits Syst Signal Process 41, 6672–6693 (2022). https://doi.org/10.1007/s00034-022-02118-z
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DOI: https://doi.org/10.1007/s00034-022-02118-z