Skip to main content
SpringerLink
Log in

Energy-Efficient VLSI Squarer Unit with Optimized Radix-2m Multiplication Logic

  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

Multipliers are demanded in a variety of applications. They consume higher power than other blocks. On the other hand, squarer units are less complex than a general-purpose multiplier, with wide use in cryptography, image processing, and video coding. This paper presents a new radix-2m squarer unit. It uses the essential sum trees to avoid redundant operations. Omitting some duplicate multiplications simplifies the final VLSI architecture. This work uses the radix-2m squarer units with m equal to 2 (radix-4), 3 (radix-8) and 4 (radix-16). We evaluate the proposed squarer units using high-efficiency video coding (HEVC) and cryptography algorithms for a range of bits. For performance results, the architectures use random input vectors. The results show that radix-4 and radix-8 units are more area and power efficient than radix-16 units. Moreover, the high energy savings of our proposed radix-4 and radix-8 units are preserved in the case studies addressed, compared to squarer units from the literature. Particularly, we show that radix-4 and radix-8 provide more energy savings in computing sum of squared differences (SSD). Furthermore, radix-4 and radix-8 squarer units are also efficient in the Montgomery-ladder architecture, reducing energy by 58.76% (radix-8) and 63.39% (radix-4) compared to the multiplier automatically selected by the logic synthesis tool.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8

Similar content being viewed by others

References

  1. A. Banerjee, D. K. Das, Squarer design with reduced area and delay, in 2015 19th International Symposium on VLSI Design and Test (2015). pp. 1–6

  2. A. Banerjee, D. Das, A new squarer design with reduced area and delay. in 19th International Symposium on VLSI Design and Test (VDAT), Avignon (2016). pp. 205–214

  3. S. Bui and J. Stine, Additional optimizations for parallel squarer units. in IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne VIC, Australia (2014)

  4. S. Bui, J. Stine, M. Sadeghian, Experiments with high speed parallel cubing units. in IEEE Computer Society Annual Symposium on VLSI, Tampa,FL, USA (2014)

  5. Cadence. (2017) Rtl compiler. https://www.cadence.com/

  6. J. Coron, Resistance against differential power analysis for elliptic curve cryptosystems. in Conference on Cryptographic Hardware and Embedded Systems(CHES) (1999). p. 292–302

  7. L. Dadda, Some schemes for parallel multipliers, Alta Frequenza (1965)

  8. T. Fontanari, G. Paim, L. Rocha, G. Santana, E. da Costa, S. Bampi, A fast monolithic 8–2 adder compressor circuit. J. Integr. Circ. Syst. 14(1), 1–7 (2019)

    Article  Google Scholar 

  9. G. Ganesh, V. Charishma, Design of high speed vedic multiplier using vedic mathematics techniques. in International Journal of Scientific and Research Publications (2012)

  10. M. Hisham, S. Yaakob, R. Raof, A. Nazren, N. Embedded, Template matching using sum of squarer unit difference and normalized cross correlation. in IEEE Student Conference on Research and Development (SCOReD) (2015)

  11. R. Jaikumar, M. Karpagam, L. Raju, A novel approach to implement high speed squaring circuit using ancient vedic mathematics techniques. Int. J. Appl. Eng. Res. 10, 1–6 (2015)

    Google Scholar 

  12. M. Joye, Highly regular mary powering ladders. in Springer (2009), p. 350–363

  13. D. Kumar, A. Kumar, Hardware implementation of 16 * 16 bit multiplier and square using vedic mathematics. in International Conference on Signal, Image and Video Processing (ICSIVP) (2012)

  14. A. Liddicoat, M.J. Flynn, “Parallel square and cube computations,” in Signals, Systems and Computers, 2000. Conference Record of the Thirty-Fourth Asilomar Conference on (2000). p. 1325–1329

  15. K. ManikanttaReddy, M.H. Vasantha, Y.B. NithinKumar, D. Dwivedi, Design of approximate booth squarer for error-tolerant computing. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 28(5), 1230–1241 (2020)

    Article  Google Scholar 

  16. T. Messerges, E. Dabbish, R. Sloan, Power Analysis Attacks of Modular Exponentiation in Smart Cards (Springer, Berlin, 1999)

    MATH  Google Scholar 

  17. P.L. Montgomery, Speeding the pollard and elliptic curve methods of factorization. Math. Comput. 48(177), 243–264 (1987)

    Article  MathSciNet  MATH  Google Scholar 

  18. S. Ourselin, X. Pennec, R. Stefanescu, G. Malandain, N. Ayache. Robust registration of multi-modal medical images: Towards real-time clinical applications. (Doctoral dissertation, INRIA) (2001)

  19. M. Poornima, K. Shivaraj, S. Shivukuma, H. Sanjay, Implementation of multiplier using vedic algorithm. in International journal of innovative technology and exploring engineering (IJITEE) (2013)

  20. S. Ramachandran, S. Kirti, Design, implementation and performance analysis of an integrated vedic multiplier architecture. in International Journal of Computational Engineering Research (IJCER) (2012)

  21. M. Ramalatha, K. Thanushkodi, D. Deena, P. Dharani, A novel time and energy efficient cubing circuit using vedic mathematics for finite field arithmetic. in International Conference on Advances in Recent Technologies in Communication and Computing, Kottayam, Kerala, India (2009)

  22. M. Rosa, G. Paim, L. Rocha, E. da Costa, and S. Bampi, The radix-\(2^{m}\) squared multiplier, in 27th IEEE International Conference on Electronics,Circuits and Systems (2020)

  23. J. Rudagi, V. Amblr, V. Munavalli, R. Patil, V. Sajjan, Design and implementation of efficient multiplier using vedic mathematics. in 3rd International Conference on Advances in Recent Technologies in Communication and Computing (ARTCom 2011) (2011)

  24. D. Sharath, G. Devaraju, C. Kavitha., Optimization and implementation of parallel squarer. IJRET

  25. M. Sharma and G. Singh, Design and fpga implementation of optimized 32-bit vedic multiplier and square architectures. in International Conference on Industrial Instrumentation and Control (ICIC) (2015)

  26. P. Shivaraj, Implementation of multiplier using vedic algorithm, Int. J. Innova. Technol. Explor. Eng. (IJITEE) (2013)

  27. L. Stefano, S. Mattoccia, Fast template matching using bounded partial correlation. Mach. Vis. Appl. 13(4), 213–221 (2003)

    Article  Google Scholar 

  28. A. Strollo, D. De Caro, Booth folding encoding for high performance squarer circuits. IEEE Trans. Circ. Syst. II Anal. Digital Signal Process. 50(5), 250–254 (2003)

    Google Scholar 

  29. K. Vaithiyanathan, S. Venkatesan, S. Sivaramakrishnan, S. Siva, Simulation and implementation of vedic multiplier using vhdl code. in International Journal of Scientific and Engineering Research (2013)

  30. C. Wallace, A suggestion for fast multiplier. IEEE Trans. Eletron. Comput. 1, 14–17 (1964)

    Article  MATH  Google Scholar 

Download references

Author information

Author notes

  1. Eduardo A. C. da Costa, Leandro Giacomini Rocha, Guilherme Paim and Sergio Bampi have contributed equally to this work.

Authors and Affiliations

  1. Graduate Program in Electronics and Computer Engineering, Catholic University of Pelotas, Pelotas, Rio Grande do Sul, Brazil

    Morgana M. A. da Rosa & Eduardo A. C. da Costa

  2. Graduate Program in Microelectronics, Federal University of RGS, Porto Alegre, Rio Grande do Sul, Brazil

    Leandro Giacomini Rocha, Guilherme Paim & Sergio Bampi

Authors
  1. Morgana M. A. da Rosa
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Eduardo A. C. da Costa
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Leandro Giacomini Rocha
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Guilherme Paim
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Sergio Bampi
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Morgana M. A. da Rosa.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

da Rosa, M.M.A., da Costa, E.A.C., Rocha, L.G. et al. Energy-Efficient VLSI Squarer Unit with Optimized Radix-2m Multiplication Logic. Circuits Syst Signal Process 42, 828–852 (2023). https://doi.org/10.1007/s00034-022-02235-9

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-022-02235-9

Keywords

Search

Navigation