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An On-Chip Trainable and Scalable In-Memory ANN Architecture for AI/ML Applications

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Abstract

Traditional von Neumann architecture-based processors become inefficient in terms of energy and throughput as they involved separate processing and memory units, also known as memory walls. The memory wall problem is further exacerbated when massive parallelism and frequent data movement are required between processing and memory units for real-time implementation of artificial neural networks (ANNs) that enable many intelligent applications. One of the most promising approach to address this problem is to perform computations inside the memory core that enhances the memory bandwidth and energy efficiency. This paper presents an in-memory computing architecture for ANN enabling artificial intelligence (AI) and machine learning (ML) applications. The proposed architecture utilizes a standard six-transistor (6T) static random access memory (SRAM) core for the implementation of a multilayered perceptron. Our novel on-chip training and inference in-memory architecture reduces energy cost and enhances throughput by simultaneously accessing the multiple rows of SRAM array per pre-charge cycle by eliminating frequent data access. The proposed architecture was trained and tested on the IRIS dataset and was observed to consume ≈ 22.46 × less energy/decision compared to earlier DIMA-based classifiers.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, National Institute of Technology Patna, Patna, India

    Abhash Kumar, Sai Manohar Beeraka & Bharat Gupta

  2. Department of Electrical Engineering, Indian Institute of Technology Patna, Bihta, India

    Jawar Singh

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  1. Abhash Kumar
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  2. Sai Manohar Beeraka
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Correspondence to Abhash Kumar.

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Kumar, A., Beeraka, S.M., Singh, J. et al. An On-Chip Trainable and Scalable In-Memory ANN Architecture for AI/ML Applications. Circuits Syst Signal Process 42, 2828–2851 (2023). https://doi.org/10.1007/s00034-022-02237-7

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